Loss of lock in the PLL of ALTLVDS_Rx

[Altera_Forum]

Hi, 

I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and connectors). Two boards are connected by two SATA cables. Accidentally (it may be very sparse), I see the loss of lock in the PLL of ALTLVDS_Rx (I capture falling edge of output "rx_locked").   What can be the reason of it ?

[Altera_Forum]

Do I understand right, that you are sending the clock over the second differential pair with the data? Did you provide correct termination for the LVDS signals? Are you able to check level and waveforms at the receiver?

[Altera_Forum]

Yes,  

SATA cable consists of two diff pairs. And I use one of them to transmit data and the second pair to transmit clock. One SATA cable is assigned to transmit from board "A" to board "B". The second SATA cable is assigned to transmit from board "B" to board "A". Termination is correct, 100 Ohm SMT resistors (for data and clock pairs respectively) at the receiver.  Data rate is 160 Mbps. Unfortunately, I have no special oscilloscope to view waveform at the receiver. Before production of PCB simulation was made to set impedance of pathes to 50 Ohm.

[Altera_Forum]

Also, Quartus II posts message after compilation: 

Critical Warning: PLL"altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_9hi1:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_90".   It may be the possible reason of loss of lock in the PLL of receiver. But Pin 90 is dedicated clock input (CLK14) in EP3C16Q240C8 and I connected external clock generator (20 MHz) to pin 90.   What pin of EP3C16Q240C8 I need to connect external clock generator ?   How can I determine a dedicated (not remote) clock input pin for PLL used in ALTLVDS_Tx?

[Altera_Forum]

The warning should be irrelevant in my opinion, because delay skew isn't an issue here and particularly not causing locss of lock. 

 I'm not sure what's forcing the choice of a TX PLL in your design, most likely a dedicated clock output used for the clock signal transmitted to the receiver. Otherwise Quartus would choose the PLL according to the clock input, if the related PLL isn't already assigned in the design. The clock resource matrix can be seen in the device manual.  A PLL clocked by another PLL (as it's the case with the RX PLL) should be set to high bandwidth according to the device manual. I'm not sure if this done by Quartus autmatically, check the PLL settings in the compiler report.

[Altera_Forum]

The PLL settings of ALTLVDS_Tx are follows (taken from report of compilation): 

 Info: Instantiated megafunction "altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component" with the following parameter:   Info: Parameter "common_rx_tx_pll" = "ON"  Info: Parameter "deserialization_factor" = "8"  Info: Parameter "implement_in_les" = "ON"  Info: Parameter "inclock_data_alignment" = "UNUSED"  Info: Parameter "inclock_period" = "50000"  Info: Parameter "inclock_phase_shift" = "0"  Info: Parameter "intended_device_family" = "Cyclone III"  Info: Parameter "lpm_type" = "altlvds_tx"  Info: Parameter "number_of_channels" = "1"  Info: Parameter "outclock_alignment" = "UNUSED"  Info: Parameter "outclock_divide_by" = "4"  Info: Parameter "outclock_duty_cycle" = "50"  Info: Parameter "outclock_multiply_by" = "1"  Info: Parameter "outclock_phase_shift" = "0"  Info: Parameter "output_data_rate" = "160"  Info: Parameter "pll_self_reset_on_loss_lock" = "OFF"  Info: Parameter "registered_input" = "TX_CORECLK"  Info: Parameter "use_external_pll" = "OFF"

[Altera_Forum]

Also, there is a very interesting moment in report: 

Info: Parameter "outclock_divide_by" = "4"  But in Wizard of ALTLVDS I configured "outclock divide factor = 8" !!!  It is obvious disagreement which may be the bug of Quartus II.

[Altera_Forum]

I use GXO-7531 (Golledge) as external clock generator. Its features are: frequency = 20 MHz, frequency stability = 100 ppm. 

 May be 100 ppm is bad with relation to jitter ?

[Altera_Forum]

Frequency stability of a crystal oscillator doesn't tell much about it's jitter. Generally, crystal oscillator jitter is very low, except for some programmable oscillators (they may be sold as fixed frequency devices though). 

 I don't excactly understand your clocking scheme. You are operating the receiver source synchronous, with an external reference clock from the transmitter, why have you selected common rx_tx_pll?   I think, the discrepancy with outclock_divide is due to the fact that actual LVDS fast clock frequency is only half the output bit rate, and no bug.

[Altera_Forum]

Dear FvM, 

thank you for your help.  Your idea is interesting about "...selected common rx_tx_pll". I didn't emphasize this option in wizard.  Now, I have disabled option "Use shared PLL(s) for receivers and transmitters" in both ALTLVDS_Rx and ALTLVDS_Tx. And I'll try modified project tomorrow.  About clocking scheme. External clock generator is connected to pin 90 of EP3C16Q240C8. In Quartus II the signal from pin 90 feeds the main PLL which generates internal clocks for my project. Also, the signal from pin 90 is connected directly to input "tx_inclock" of ALTLVDS_Tx. As to ALTLVDS_Rx, its input "rx_inclock" is defined as differential (LVDS) and connected to pins DIFFCLK_xx (p and n) of EP3C16Q240C8. Therefore, PLL of ALTLVDS_Rx receives its clocks from another board (i.e. from output "tx_outclock" of ALTLVDS_Tx of another board).

[Altera_Forum]

--- Quote Start ---  About clocking scheme.  --- Quote End ---   Yes, that would be the standard source synchronous scheme in my understanding. That means, if the design is using both a LVDS receiver and transmitter, it would use two sepearate PLLs (respectively the Tx PLL shared with the system clock), because Rx-PLL is clocked from the transmitter and Tx-PLL locally.

[Altera_Forum]

I tried project with disabled option "Use shared PLL(s) for receivers and transmitters" in both ALTLVDS_Rx and ALTLVDS_Tx. But losses of lock in the PLL still exist. 

 The problem may be concluded in external clock generator. PDF does not contain info about jitter of GXO-7531, and this generator is rather cheap to be an excellent product.

[Altera_Forum]

Did you check the PLL bandwidth setting? I never needed to change anything, also with cascaded PLLs, but the device handbook mentions, that the bandwidth of a cascaded PLL should be set to "high". Unfortunately, it forgets to tell about the absolute bandwidth numbers.

[Altera_Forum]

I'm sorry, but I don't know how can I get information about bandwidth setting of PLL ALTLVDS_Tx and ALTLVDS_Rx.  

PLLs of ALTLVDS_Tx and ALTLVDS_Rx are configured as internal (incorporated into ALTLVDS_Tx/Rx) but not external.   Only one PLL (which generates internal clocks for my logic) is accessible to get info about bandwidth. In the section "Bandwidth/SS" of wizard it was configured as "Auto". I set it option to Preset -> "Low" but it didn't help.

[Altera_Forum]

The PLL bandwidth is reported in the compilation report. The settings under Anlysis and synthesis, parameter settings and the actual value under Fitter/Resource Section/PLL.

[Altera_Forum]

I found settings of PLL. 

 PLL of ALTLVDS_Tx: SDC pin name: inst23|altlvds_tx_component|auto_generated|lvds_tx_pll PLL mode: Normal Compensate clock: clock0 Compensated input/output pins: -- Switchover type: - Input frequency 0: 20.0 MHz Input frequency 1 - Nominal PFD frequency: 20.0 MHz Nominal VCO frequency: 639.8 MHz VCO post scale: 2 VCO frequency control: Auto VCO phase shift step :195 ps VCO multiply -- VCO divide -- Freq min lock: 9.8 MHz Freq max lock: 20.32 MHz M VCO Tap: 0 M Initial: 3 M value: 32 N value: 1 Charge pump current setting: 1 Loop filter resistance setting: 24 Loop filter capacitance setting: 0 Bandwidth: 450 kHz to 980 kHz Real time reconfigurable: Off Scan chain MIF file: -  Preserve PLL counter order: Off PLL location: PLL_1 Inclk0 signal: clk_ext Inclk1 signal - Inclk0 signal type: Dedicated Pin Inclk1 signal type -

[Altera_Forum]

PLL settings in ALTLVDS_Rx: 

 SDC pin name: inst24|altlvds_rx_component|auto_generated|lvds_rx_pll PLL mode: Source Synchronous Compensate clock: clock0 Compensated input/output pins: lvds_data_rx, lvds_data_rx Switchover type: - Input frequency 0:20.0 MHz Input frequency 1:- Nominal PFD frequency:20.0 MHz Nominal VCO frequency:639.8 MHz VCO post scale: 2 VCO frequency control: Auto VCO phase shift step: 195 ps VCO multiply: - VCO divide: - Freq min lock: 9.8 MHz Freq max lock: 20.32 MHz M VCO Tap: 0 M Initial: 3 M value: 32 N value: 1 Charge pump current: setting 1 Loop filter resistance: setting 24 Loop filter capacitance: setting 0 Bandwidth: 450 kHz to 980 kHz Real time reconfigurable: Off Scan chain MIF file: - Preserve PLL counter order: Off PLL location: PLL_2 Inclk0 signal: lvds_clock_rx Inclk1 signal: - Inclk0 signal type: Dedicated Pin Inclk1 signal type: -

[Altera_Forum]

The suggestion is to set bandwidth_type => "HIGH" instead of bandwidth_type => "AUTO" in the generic map of the RX-PLL instance.

[Altera_Forum]

Ok, thank you. 

I'm sorry, how can I get access to the generic map of the RX-PLL instance?

[Altera_Forum]

It would be used in manual instantiation of an altpll component, which is my preferred method to place a PLL. Using the ALTPLL MegaFunction through the Wizard, it's an advanced PLL parameter, as you described above. It's not available with an "internal" ALT_LVDS PLL, I think.

[Altera_Forum]

Yes,  

it is impossible with internal PLL of ALTLVDS_Rx/Tx. I need to create ALTLVDS_Rx with option "Use external PLL" turned on.  Is it what you recommend?