Compilation error in Quartus 18.1 Pro

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Compilation error in Quartus 18.1 Pro

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Hello! I have an error Quartus when compiling the project (a problem with the CLK signal).

Error(129001): Input port CLK on atom "eth_ddr_out|comp1|ALTDDIO_OUT_component|auto_generated|ddio_outa[4]", which is a twentynm_ddio_out primitive, is not legally connected and/or configured.

The CLK circuit is normally wound up. How can I fix this error?

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