Analyzers
Talk to fellow users of Intel Analyzer tools (Intel VTune™ Profiler, Intel Advisor)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
5256 Discussions

Bus Data Ready (This Processor) event

Anonymous90
Beginner
516 Views
The vtune reference guide describes Bus Data Ready (This Processor) event as follows:

This event counts the number of front-side bus clocks that the bus is transmitting data driven by the processor core, including full reads|writes and partial reads|writes and implicit writebacks.


My question is that:

1. Does this event count UC type of memory access?
2. Does this event count hardware and software prefetch?
3. I think this only counts the data access, not instruction memory access, right?
0 Kudos
0 Replies
Reply