Talk to fellow users of Intel Analyzer tools (Intel VTune™ Profiler, Intel Advisor)

DTLB Page Walks

Can somebody explain to me in plain english the problem with DTLB Page Walks.
I seem to have a confusion with it.
Basically I have a slide that states to "Check Paging Issues"
- Measure density of data access pattern with respect to 4K page
- Reads From the processor / DTLB Page Walks
- A good number is 64
o 4K/cache line size = 4K/64 bytes = 64
- Low value indicates data access pattern is inefficient
oIncur frequent DTLB miss penalty
oCan cause excess memory traffic
I have some problems swallowing this one...
Thanks in advance
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1 Reply
Honored Contributor III
Not knowing where you stand with this, I'll offer the following:
This cryptic text fragment refers to performance problems associated with data access patterns which jump around frequently among pages (4K blocks of memory). You should never have such a problem, if your memory access is all sequential, or maybe even as much as every 4th element of an array in memory. If you use only 64 items of data per page, given that size and performance of TLB is limited, this is likely to pose a performance bottleneck.
After some practice with VTune, you may be able to show whether DTLB page walks or misses are correlated with low performance in your application.
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