Community
cancel
Showing results for 
Search instead for 
Did you mean: 
jqdu
Beginner
57 Views

FSB Utilization and Traffic

Sorry for this question again.

Somehow I'm still confused about how to use Vtune to estimate the FSB utilization and traffic. I jumped into the details and read Intel's manuals, however, this is no clear explanation about this topic.

What I want is two formulas that could calculate FSB utilization and traffic, and explanations to them.

I'm playing with a machine with two Xeon Nocona processors. The following events are supported by Vtune.

128-bit MMX Instructions Retired
1st Level Cache Load Misses Retired
2nd Level Cache Load Misses Retired
2nd Level Cache Read Misses
2nd-Level Cache Read References
2nd-Level Cache Reads Hit Exclusive
2nd-Level Cache Reads Hit Modified
2nd-Level Cache Reads Hit Shared
3rd-Level Cache Read Misses
3rd-Level Cache Read References
3rd-Level Cache Reads Hit Exclusive
3rd-Level Cache Reads Hit Modified
3rd-Level Cache Reads Hit Shared
64-bit MMX Instructions Retired
64k/4M Aliasing Conflicts
All UC Underway from The Processor (AT-E)
All UC from the Processor
All WC Underway from The Processor (AT-E)
All WC from the Processor
All WCB Evictions (TI)
All calls
All conditionals
All indirect branches
All returns
Branches Retired
Bus Accesses Underway from All Agents (AT-E)
Bus Accesses Underway from The Processor (AT-E)
Bus Accesses from All agents
Bus Accesses from the Processor
Bus Data Ready from the Processor (TI)
Bus Reads Underway from The Processor (AT-E)
Clockticks
DTLB Load Misses Retired
DTLB Load and Store Misses Retired
DTLB Page Walks (TI)
DTLB Store Misses Retired
IO Reads Chunk (BSQ) (AT-E)
IO Writes Chunk (BSQ) (AT-E)
ITLB Misses
ITLB Page Walks (TI)
Instructions Completed
Instructions Retired
Loads Retired
MOB Loads Replays (AT-E)
MOB Loads Replays Retired
Machine Clear Count
Memory Order Machine Clear
Mispredicted Branches Retired
Mispredicted calls
Mispredicted conditionals
Mispredicted indirect branches
Mispredicted returns
Non-Halted Clockticks
Non-prefetch Bus Accesses from the Processor
Non-prefetch Reads Underway from The Processor (AT-E)
Packed Double-precision Floating-point Streaming SIMD Extension Instructions Retired
Packed Single-precision Floating-point Streaming SIMD Extension Instructions Retired
Reads Invalidate Full - RFO (BSQ) (AT-E)
Reads Non-prefetch Full (BSQ) (AT-E)
Reads Non-prefetch from the Processor
Reads from the Processor
Scalar Double-Precision Floating-Point Streaming SIMD Extension Instructions Retired
Scalar Single-precision Floating-point Streaming SIMD Extension Instructions Retired
Self-Modifying Code Clear
Speculative Instructions Completed
Speculative Microcode uops
Speculative TC-built uops
Speculative TC-delivered uops
Speculative Uops Retired
Split Load Replays
Split Loads Retired (AT-E)
Split Store Replays
Split Stores Retired (AT-E)
Stalled Cycles of Store Buffer Resources (Non-Standard)
Stalls of Store Buffer Resources (Non-Standard)
Stores Retired
Streaming SIMD Extensions Input Assists (TI)
TC flushes
TC to ROM Transfers
Tagged Mispredicted Branches Retired
Trace Cache Build Mode
Trace Cache Deliver Mode
Trace Cache Misses
UC Reads Chunk (BSQ) (AT-E)
UC Reads Chunk Split (BSQ) (AT-E)
UC Reads Chunk Underway (BSQ) (AT-E)
UC Write Partial (BSQ) (AT-E)
Uops Retired
WB Writes Full Underway(BSQ) (AT-E)
WCB Full Evictions (TI)
Write WC Full (BSQ) (AT-E)
Write WC Partial (BSQ) (AT-E)
Write WC Partial Underway (BSQ) (AT-E)
Writes Underway from The Processor (AT-E)
Writes WB Full (BSQ) (AT-E)
Writes from the Processor
x87 Input Assists
x87 Instructions Retired
x87 Output Assists

0 Kudos
1 Reply
Peter_W_Intel
Employee
57 Views

If you want to know data bus utilization, please find "External Bus Ratios" in Ratio Group - select "Data Bus Utilization", that is percentage of bus cycles used for transferring data among all bus agent in the system, including processors and memory. BUS_DRDY_CLOCKS.ALL_AGENTS / CPU_CLK_UNHALTED.BUS

Reply