Hi, I have a question about how performance counters measure data cache misses. I am running a benchmark that I have developed on Intel Xeon E5440. I am interested in looking at number of L1D and L2D cache misses I have seen that to measure L2D cache misses, it's possible to use Architecural performance event LLC Cache misses. I have noticed that this event counts all completed requests to a L2 cache line that it is in invalid state. But, I know that a cache miss occurs when I want to read/write a phisical address that it is not in cache.
My question is: with performance counter, is it possible to understand if I found or not my phisical address in L2 cache?
I know that I can't read data from a cache line in invalid state, this is a read miss, but I have also a read miss if I don't find the address that I'm looking for in cache, and is this situation considered by performance counters?
I have seen that also in case of L1D cache misses, performance counters counts number of accesses at L1D cache line at invalid state, but it is not only situation that cause cache misses
LLC means Last Level Cache, it indicates to L3 cache.
Yourquestion is performance counter for physical address in L2 cache. TLB is responsible to translate your physical address to virtual address, so you don't worryhow your contents of physical address works in L1/L2/LLC cache.
Both Microsoft* Debugger and Intel? VTune? Performance Analyzer display address as RVA (relative virtual address) format.
If your data is stored in an address, and this address is stored in other address. There is no difference - your address will be treated as contents and got from other address, then get your data from this address.
If you care of read/write access missing L1D, please use L1D_CACHE_ST.I_STATE; L1 data cache stores in I state L1D_CACHE_LD.I_STATE; L1 data cache read in I state