Thanks for your reply.
Yes my i3 330M is Nehalem Processor.But the link that you gave mentions that we can estimate the % of cycles due to long latency data access.
However i would like to know formulae for calculating L1/L2/L3 cache misses.
Are the formulae mentioned below correct?
1. L1: L1D_CACHE_LD.I_STATE / L1D_CACHE_LD. MESI
2. L2: (MEM_LOAD_RETIRED.LLC_UNSHARED_HIT + MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM) / L2_RQSTS.LOADS
3. L3: MEM_LOAD_RETIRED.LLC_MISS / (MEM_LOAD_RETIRED.LLC_UNSHARED_HIT + MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM)
Above formulas are good in my view, you can use anythreshold - for example, .2 tojudge the result is good or bad.
Referring to the threadhttp://software.intel.com/en-us/forums/showthread.php?t=71832i found
L1 data cache miss rate= MEM_LOAD_RETIRED.L1D_MISS/
For L2 data cache miss = MEM_LOAD_RETIRED.L2_MISS event/
Are these for core 2 duo processors?
Please also mention what is the difference between MEM_LOAD_RETIRED.L1D_MISS event, and L1D_CACHE_LD.I_STATE event.
The ratio is defined by user,Misses can be divided by L1/L2/L3 access, INST_RETIRED, (with penalty) CPU_CLK_UNHALED, MEM_INST_RETIRED.LOADS, etc.
It depends onyour needs.