what is dual sectored line in the cache info?

[vtuneuser]

What is the feature of "dual-sectored line" in the Intel Xeron processor L1/L2/L3 caches? Is there any diagram?

Thanks.

[TimP]

You may be referring to the default setting of "Adjacent Sector Prefetch", which brings pairs of 64-byte cache lines into cache on read. When you have a read in either the odd or even numbered cache line, prefetch of the other line of the pair is triggered.

[vtuneuser]

This is my calculation, L1 size=8192bytes, the cacheline size is 64k, so there are 128 cachelines with 4-way associatives in L1, i.e. 32 sets, why there are 64 entries in Data TLB instead of 32 entries? is this why was called "dual sectored line" for prefetch to gain the performance?

[vtuneuser]

sorry, correction the cacheline size is 64 bytes, not 64k.