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Welcome to the cutting-edge world of chiplet technology[1], where the Universal Chiplet Interconnect Express (UCIe) is revolutionizing on-package connectivity. UCIe is not just any standard—it's a game changer, delivering high-speed, energy-efficient, cost-effective links between chiplets[2]. Solutions across the computing spectrum from mobile to automotive to datacenter to AI can increase innovation and reduce time to market by leveraging chiplets that are built with open-standard-based interconnects.
With more than 130 member companies who are leading suppliers and consumers of chiplet-based architectures, the UCIe specification has been evolving to address the needs of next generation chip designs. UCIe 2.0 builds upon the foundation of the UCIe 1.0/1.1 specifications and is fully backwards compatible. With UCIe 2.0, we're tackling the complexities of multi-chiplet systems head-on, helping to ensure everything from manageability to testing is being built into the specification. And for those who like to push boundaries, UCIe-3D offers ultra-fine pitches and hybrid bonding.
Figure 1: A rendering shows multiple chiplets connected with a combination of 2D and 3D packaging techniques to create a complex system in a package.
Evolving the UCIe Standard
UCIe 2.0 marks a significant leap forward in the realm of 3D packaging[3], setting the stage for a transformative increase in bandwidth density and power efficiency. This evolution is not just about stacking chips; it's about redefining the very fabric of system architecture. By enabling a vertical labyrinth of interconnected chiplets, UCIe 2.0 promises a future where data highways are more compact yet vastly more efficient, allowing for a surge in processing power without the penalty of increased energy consumption. This is the kind of innovation that propels industries forward, offering system designers the tools to build the next generation of electronic devices that are both powerful and energy conscious.
At the heart of UCIe 2.0 lies a comprehensive approach to the manageability, debugging, and testing of multi-chiplet system-in-package constructions. This holistic management can ensure that as systems grow more complex, their maintainability and reliability scale accordingly. The specification introduces improved system-level solutions, integrating manageability directly into the chiplet stack, which streamlines the entire design process.
Characteristics/KPIs | UCIe-S | UCIe-A | UCIe-3D | Comments for UCIe-3D |
Target for Key Metrics | ||||
BW Density (GB/s/mm2) | 22 – 125 | 188 – 1350 | 4000 at 9µm | 4TB/s/mm2 @ 9µm, ~12TB/s/mm2 @ 5µm, ~35T/s/mm2 @ 3µm, ~300T/s/mm2 @ 1 µm |
Power Efficiency Target (pJ/b) | 0.5 | 0.25 | <0.05 at 9µm | Conservatively estimated at 9µm pitch <0.02 for 3µm pitch |
Table 1: Select KPIs for UCIe 1.0 and UCIe 2.0 (SourceL UCIe Consortium)
With ball map optimizations and work-in-progress automotive enhancements, UCIe 2.0 is not only setting the standard for today's requirements but is also paving the way for the future demands of the automotive industry. The commitment to optimized package designs furthers interoperability and simplifies compliance testing, all while maintaining full backward compatibility with UCIe 1.1 and 1.0, helping ensure a seamless transition for existing UCIe adopters.
The latest enhancements in manageability and design-for-excellence (DFx) reflect our ongoing mission to refine and advance the full range of needs for the system lifecycle, while the advent of UCIe-3D showcases our readiness to embrace the challenges that come with groundbreaking leaps in power-efficient performance.
Intel’s Commitment to UCIe
The UCIe specification brings together very competitive performance advantages to multi-die system designers. These advantages make UCIe a compelling technology poised to ease the path toward a truly open multi-die system ecosystem by enabling interoperability.
UCIe consortium members have been showcasing products and live demos rooted in the UCIe 1.0 and 1.1 specs. This is the dawn of a new era, with UCIe 2.0 standing as a testament to this promise to continue evolving the specifications with industry input to help meet the needs of the evolving chiplet-based market.
Intel is committed to advancing the UCIe standard in partnership with industry leaders who share the goal to define a robust open ecosystem. As Intel Products incorporate chiplets, and Intel Foundry customers seek systems foundry capabilities for chiplet-based die and packaging, we believe that UCIe will be key to fuel innovative system-in-package products.
For more information on UCIe 2.0, please visit https://www.uciexpress.org/. For questions about support for designing and building chiplets for your application, contact your Intel representative.
[1] Learn more Intel Foundry’s chiplet strategy at https://www.intel.com/content/www/us/en/foundry/chiplets.html.
[2] https://www.nature.com/articles/s41928-024-01126-y
[3] Learn more about Intel Foundry’s advanced packaging offerings at https://www.intel.com/content/www/us/en/foundry/packaging.html.
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