By Lori Scott, Senior Director of Marketing, Intel Foundry
Intel and Intel Foundry researchers have demonstrated a breakthrough in metal-insulator-metal (MIM) capacitor material options for on-chip decoupling that could solve a critical challenge in advanced semiconductor manufacturing: maintaining stable power delivery as transistors continue shrinking. Presented this week at the 2025 IEEE International Electron Devices Meeting (IEDM), December 6-10, the team shared three promising MIM stack materials — ferroelectric hafnium zirconium oxide (HZO), titanium oxide (TiO), and strontium titanate (STO) — in deep-trench capacitor structures compatible with standard backend-of-the-line chipmaking processes. These MIM options deliver 60 to 98 femtofarads per square micrometer (fF/μm2) of planar capacitance, representing a multi-generational leap over state-of-the-art technology, while maintaining exceptional reliability with leakage levels 1,000 times lower than industry targets [1].
In other technical and tutorial sessions, Intel Foundry researchers and collaborators presented the following topics:
- Ultra-thin GaN chiplet technology: Researchers have demonstrated the world's first complete gallium nitride (GaN) chiplet technology based on 300-millimeter (mm) silicon wafers. This breakthrough features an ultra-thin chiplet measuring just 19 micrometers (µm) — thinner than a human hair — along with a complete library of integrated digital control circuits. This innovation addresses challenges in power delivery and efficiency for next-generation high-performance power and radio frequency (RF) electronics.
- Silent data errors: This invited talk presents how traditional manufacturing tests miss critical defects that cause silent data corruption in data center processors, requiring diverse functional testing to ensure reliability at scale.
- Reliability of scaled 2D FETs: With Technical University of Vienna, researchers explored whether 2D materials like molybdenum disulfide (MoS₂) can replace silicon in the future for miniaturized transistors.
- Selective edge processes in 2D FETs: With IMEC, researchers improved fab-compatible modules for source/drain contact formation and gate stack integration with reduced equivalent oxide thickness (EOT).
- CMOS scaling: With Seoul National University, this tutorial covers the latest advances in complementary metal–oxide–semiconductor (CMOS) scaling technologies. Learn how power/performance/area considerations, back-side power delivery networks, and design-technology co-optimization are shaping semiconductor development for artificial intelligence (AI) and high-performance computing (HPC).
Learn more about Intel and Intel Foundry’s innovative technology research in the following IEDM sessions.
Technical Sessions with Intel Presenters
Intel Foundry
Promising MIM capacitor options ranging from ferroelectric HZO to ultra high-k dielectric materials such as TiO and STO are demonstrated for decoupling capacitor (DCAP) applications. These options offer a multi-generational capacitance boost over state-of-the-art without compromising reliability metrics such as leakage, capacitance drift, and breakdown. This work demonstrates the potential of a range of MIM capacitance density enhancements, which are both stable and low leakage, for next-generation advanced CMOS technologies.
GaN Chiplet Technology Based on 300 mm GaN-on-Silicon
Intel Foundry
Intel Foundry researchers demonstrate for the first time a GaN chiplet technology based on 300 mm GaN-on-silicon process for high-performance, high-density, efficient power electronics and high-speed RF electronics. This GaN chiplet technology features: (a) Industry’s thinnest GaN chiplet with an underlying silicon substrate that is only 19 µm thick, harvested from a fully-processed, thinned and singulated 300 mm GaN-on-silicon wafer; (b) Industry’s first library of fully-functional integrated on-die CMOS digital circuits, from logic-gates, multiplexers, and flip-flops to ring-oscillators, using a monolithically integrated GaN N-type metal-oxide-semiconductor high-electron-mobility transistor (N-MOSHEMT) and silicon p-channel metal-oxide-semiconductor field-effect transistor (Si PMOS) process; (c) Promising results in time-dependent dielectric breakdown (TDDB), positive bias temperature instability (pBTI), high-temperature reverse bias (HTRB) and hot-carrier injection (HCI) studies indicate that the 300mm GaN MOSHEMT technology can meet required reliability metrics.
Intel
Multiple industry studies have shown that silent data errors (SDE) or other forms of silent data corruption (SDC) caused by manufacturing defects may occur on system-on-chip (SoC) devices deployed at-scale in data centers. While structural test techniques such as scan are an essential component of manufacturing tests, system-based functional testing is required to deliver SoCs that meet cloud data center quality demands. This research shares results obtained from multiple generations of server SoCs that illustrate the importance of using a large set of diverse functional tests, such as those included in the Intel® Data Center Diagnostic Tool (Intel® DCDiag) test suite, to screen defects that manifest as SDE.
Technical Sessions with Collaborators
From Planar to Gate-All-Around: Stability and Reliability of Scaled 2D FETs
Technical University of Vienna and Intel Foundry
Two-dimensional (2D) channels could potentially outperform silicon in the ultimately scaled complementary field-effect transistor configuration. However, forming a high-quality interface between layered van der Waals (vdW) channels and the gate oxide remains a major challenge for 2D FETs. In this study, we comprehensively test the stability and reliability of two transistor technologies: planar and gate-all-around (GAA) FETs. Both feature a 1-L MoS2 channel and a gate stack of amorphous hafnium dioxide (HfO2): 4.3 nm for planar and 4.5 nm for GAA. The GAA, however, are scaled 2D FETs with nanometer-range dimensions, enabling observation of single atomic charge trapping events. The main objective of this study is to compare these technologies in terms of hysteresis, bias temperature instability (BTI), and random telegraph noise (RTN) measurements, which together offer a better understanding of the trap physics within the oxide and at the channel/insulator interface.
IMEC and Intel Foundry
Two rarely used features of transition metal dichalcogenides (TMDs) are their exceptional chemical stability in some wet etchants and their unique anisotropic van der Waals structure. These are leveraged to selectively recess the oxide cap, and fabricate 2D FETs with damascene-type top contacts on monolayers tungsten disulfide (WS2) and MoS2, and multilayer tungsten diselenide (WSe2) in a 300 mm pilot line. In addition, the process is extended to a replacement oxide stack, and interlayer selective removal is demonstrated using liquid intercalation, reducing the top gate capacitive equivalent thickness (CET) from 2.5 to 1.5 nm. These form three new fundamental building blocks for 2D integration technology.
Tutorial Session
Advances in CMOS Technologies and Cell Height Scaling Considerations
Intel Foundry and Seoul National University
AI has seen a tremendous jump in capability and drastically expanded application areas in the last few years. CMOS technology is essential in building HPC systems for AI applications. This tutorial focuses on the latest advances on CMOS scaling from fin field-effect transistor (FinFET) technology, nano-sheet or GAA, dielectric separated N-P sheet or fork-sheet to stacked N-P nano sheet or complementary field-effect transistor (CFET). Due to the increased pace and demand, additional scaling considerations such as cost and time to market have been added on top of power/performance/area. The overall scaling considerations will strongly affect process optimization of all critical dimensions around the active transistor and backend-of-the-line dimensions. Back-side power delivery network (BSPDN) offers an additional power/performance scaling/optimization point. Within a process node, design technology co-optimization (DTCO) methodology plays an increasingly important role in performance offerings and design for manufacturing optimization.
Find out how Intel Foundry’s innovative technologies can help you bring your products to life. Reach out to us at foundry.contact@intel.com.
Endnotes
- “Next-Generation Embedded Decoupling Capacitors for Advanced CMOS Technology: From Ferroelectrics to Ultra High-k Dielectrics,” IEEE International Electron Devices Meeting, December 2025.
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