Posted on behalf of Anil Nanduri
We have a multi-year HPC roadmap that will deliver a diverse portfolio of heterogeneous architectures. These architectures, planned through 2024, will allow us to improve performance by orders of magnitude while reducing power demands across both general-purpose and emerging workloads such as AI, encryption and analytics.
Here’s a sampling of the advancements we have planned:
- Delivering the Intel® Xeon® processor code-named Sapphire Rapids with High Bandwidth Memory (HBM) leverages advanced packaging technologies and silicon innovations to bring substantial performance, bandwidth and power-saving improvements for HPC,
- Unleashing memory bandwidth-bound workloads while delivering significant performance improvements across key HPC use cases, and
- Increasing compute density to push for orders of magnitude performance gains across HPC and AI supercomputing workloads.
One instantiation of these advancements is our first flagship Intel data center graphics processing unit (GPU), code-named Ponte Vecchio, which is already outperforming competition for complex financial services applications and AI inference and training workloads. And we have already announced our successor to this powerhouse data center GPU, code-named Rialto Bridge, which will offer significantly increased density, performance and efficiency, while providing software consistency.
We also recently discussed Falcon Shores, the next major architecture innovation on our roadmap, bringing x86 CPU and Xe GPU architectures together into a single socket.
I encourage you to see the ISC 2022 keynote video and blog from Jeff McVeigh, Vice President and General manager of the Super Compute Group, where he provides additional details of these advancements.
