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Highlights
- Intel Labs and collaborators from the University of Pennsylvania, Carnegie Mellon University, and IS4S have been selected by DARPA to perform in the H6 program to develop a GPS-independent tactical-grade clock with microsecond timing precision.
- Intel Labs will leverage its experience with MEMS oscillators and machine learning to design the tactical-grade clock.
Mission success in military operations can often come down to a mere millionth of a second. Current military systems that rely on global positioning system (GPS) timing updates are vulnerable to GPS’s unreliability underground or underwater and its susceptibility to adversarial signal jamming, rendering the system degraded or unavailable. When GPS is not available or denied, clock drift can adversely affect timing precision, ultimately reducing the effectiveness of military operations and degrading situational awareness. Denied GPS synchronization can severely affect commercial operations, from network synchronization to navigation. To help overcome these limitations, Intel Labs and collaborators from the University of Pennsylvania, Carnegie Mellon University, and IS4S have been selected by the Defense Advanced Research Projects Agency (DARPA) to perform in the H6 program to develop a GPS-independent tactical-grade clock that sustains weeklong microsecond timing while maintaining signal assurance, pervasive security, and high-bandwidth communications.
“We are excited for the opportunity to try to solve such a hard problem that is critical for both Department of Defense needs as well for our core commercial products,” said Mohamed Abdel-moneum, an Intel Labs principal engineer in the RF Platform Technologies group and principal investigator for the H6 program.
The DARPA H6 program is the modern equivalent of the British Parliament’s 1714 Longitude Act competition, which offered a £20,000 prize for any method capable of maintaining knowledge of longitude to one-half degree over the course of a six-week voyage from Britain to the West Indies. Clockmaker John Harrison developed five generations of clocks, which he called “H1” through “H5,” the latter representing the first marine chronometer capable of maintaining the necessary accuracy.
While the longitude problem was the most important positioning, navigation, and timing (PNT) challenge during the 1700s, GPS denial is the greatest problem today, according to DARPA. Ubiquitous, compact timing is critical for navigation, communications, and electronic warfare, as well as intelligence, surveillance, and reconnaissance (ISR) on low size, weight, and power (SWaP) platforms.
Compact timing is currently disseminated via GPS, which conditions local oscillators to maintain timing between GPS updates. Ultra-small, low-power, fieldable clocks that can maintain their microsecond timing precision for one week over an operating range of -40 to 85 Celsius without GPS fixes would remove GPS-timing dependence for the majority of Department of Defense (DoD) missions. Today, no such fieldable tactical-grade clock exists. While some clocks can achieve the necessary performance, their SWaP precludes their use in a tactical setting.
Using MEMS Oscillators and Machine Learning for Precision Timing
To design the tactical-grade clock, Intel Labs will leverage its experience working with microelectromechanical systems (MEMS) oscillators from previous collaborations with Sandia National Laboratories, a federally funded research and development (FFRDC) Department of Energy (DOE) laboratory funded under a DoD program. Recent advances in MEMS timing technology have focused on resonators fabricated with multiple materials, which can fully cancel the first-order temperature coefficient around a selectable set point while reducing higher order effects. Designs also have been proposed to reduce the impact of stress relaxations by localizing the stresses away from the active resonator components. The MEMS oscillators have the power, volume, and cost advantages but not the temperature and aging stability required under the H6 program.
The team is taking a novel approach by using machine learning as a new degree of freedom in the design space to bridge the performance gap of the MEMS oscillators while capitalizing on the size, weight, power, and cost (SWaP-C) advantages to compensate for aging-induced clock drift. The model learns the behavior of the MEMS oscillator while GPS is available, and then compensates for the drift of the MEMS oscillator when GPS is denied.
Intel Labs began work on the three-phase program on April 12. Phase 1 addresses both clock dependence on temperature and SWaP reduction while Phase 2 focuses on clock aging with operation demonstrated throughout the tactical temperature range. In Phase 3, performers are expected to demonstrate a fully integrated tactical-grade clock, and the fabrication and delivery of five clocks.
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Scott Bair is a Senior Technical Creative Director for Intel Labs, chartered with growing awareness for Intel’s leading-edge research activities, like AI, Neuromorphic Computing and Quantum Computing. Scott is responsible for driving marketing strategy, messaging, and asset creation for Intel Labs and its joint-research activities. In addition to his work at Intel, he has a passion for audio technology and is an active father of 5 children.
Scott has over 23 years of experience in the computing industry bringing new products and technology to market. During his 15 years at Intel, he has worked in a variety of roles from R&D, architecture, strategic planning, product marketing, and technology evangelism. Scott has an undergraduate degree in Electrical and Computer Engineering and a Masters of Business Administration from Brigham Young University.