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Intel 3 Process, Quantum, and Photonics Highlighted at 2024 VLSI Symposium

ScottBair
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Scott Bair is a key voice at Intel Labs, sharing insights into innovative research for inventing tomorrow’s technology.

Highlights

  • Intel researchers will present 11 papers at the 2024 IEEE Symposium on VLSI Technology & Circuits, taking place on June 16-20.
  • Many papers feature Intel Foundry technology, including advanced Intel 3 FinFET technology performance gains compared to Intel 4, and clocking and power delivery for future heterogeneous 2.5 and 3D systems.
  • Other topics include research on a quantum computing millikelvin qubit control chip and a silicon photonics co-packaged optical receiver.

Intel engineers and researchers had 11 papers accepted at the 2024 IEEE Symposium on VLSI Technology & Circuits on June 16-20. The symposium highlights advanced technology developments, innovative circuit designs, and their respective applications. Many papers feature Intel Foundry technology, including Intel 3 FinFET technology demonstrating up to 18% performance gain at iso-power over Intel 4, and clocking and power delivery for future heterogeneous 2.5 and 3D systems. Other topics include research on using traditional CMOS circuits for qubit control at millikelvin temperatures to enable quantum computing scaling to millions of qubits, and a silicon photonics co-packaged optical receiver based on Intel’s in-house silicon photonics technology.

Advanced Intel 3 FinFET Process and Performance Gains

T1.1 An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications

Intel 3 FinFET technology has been optimized to provide 10% logic scaling, a full node of performance improvement and improved reliability compared to Intel 4. Through transistor enhancements, interconnect optimization, and design co-optimizations up to 18% performance gain at iso-power is achieved over Intel 4.

Clocking and Power Delivery for Future Heterogeneous 2.5 and 3D Systems

T9.1 Integration of Si-Interposer and High Density MIM Capacitor on 2.5D Foveros Face-to-Face Architecture

Integration of different computing elements through silicon interposers enables scaling opportunities beyond Moore’s law. Intel’s passive Si-Interposer enables interconnections among different chiplets using through silicon via (TSV) technology along with a refined 36μm micro-bump pitch in a face-to-face die configuration. The Si-Interposer houses a high-density metal-insulator-metal (HDMIM) integrated decoupling capacitor for voltage droop reduction and noise suppression. Products can either utilize HDMIM in the Si-Interposer die, a built in HDMIM in the chiplet die, or both. Paper describes HDMIM fabrication steps, electrical properties, reliability benchmarks, and performance enhancements by incorporation of Si-Interposer HDMIM.

C11.4 A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems

We present a resonant clocking technique featuring rotary traveling wave oscillators (RTWOs) and a rotary oscillatory array (ROA) in Intel 4 CMOS for high-frequency, low-jitter, low-power, and low-skew clock generation and distribution in 3D heterogeneous multi-die systems. The active base die incorporates an array of four coupled RTWOs capable of dynamic frequency tuning. Three independent resonant rotary rings are implemented to demonstrate the range of native resonant frequencies with very low jitter. The circuits operate across a wide frequency (3.2GHz-15GHz) and voltage (0.55V-1.2V) range with very low measured period jitter (107fs-705fs) and minimal duty-cycle distortion (50±0.8%) suitable for multi-die high-performance GPUs.

C17.1 A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs

This paper presents a monolithic Multi-stage Modular Switched Capacitor Voltage Regulator (MMSCVR) in 16nm CMOS with scalable design (up to 7A), self-timed deadtime generator, and safe startup for vertical power delivery in heterogeneous 3D-ICs. The proposed MMSCVR demonstrates 90.6% peak efficiency and 5.7A/mm2 peak current density with a 3V-to-1V conversion – 4.9x higher than state-of-the-art. It is also the first monolithic 4V-to-1V MMSCVR, achieving 7.8x higher current density than prior arts with off-chip capacitors.

Quantum Computing Qubit Control Chip

C26.1 A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of Silicon Qubit Gates

Large-scale silicon qubit control requires closer integration of control electronics to qubits at the mK stage of the dilution refrigerator to address the wiring bottleneck. We present a mK demultiplexer chip that uses only two input analog voltages and digital control signals, to provide both DC bias and high-speed voltage pulsing for up to 64 qubit terminals. Integrated with a foundry qubit chip on the same PCB and controlled by a 4 K cryo-CMOS controller, mK cryogenic measurements show multi-terminal characterization of a qubit device.

Silicon Photonics Co-Packaged Optical Receiver

C14.4 A 4x50Gb/s NRZ 1.5pJ/b Co-Packaged and Fiber-Terminated 4-Channel Optical RX

This paper presents a 4-channel co-packaged optical RX that integrates a photodiode array, fiber termination, and a transimpedance amplifier front end (TIA-FE) IC on the same package as an RX data-path IC. To achieve high sensitivity, the TIA-FE employs bandwidth extension and in-band group delay compensation techniques that are co-optimized with a ¼-rate 2-tap feed-forward equalizer (FFE) in the RX data-path. A StrongArm latch that improves noise variance by 3.5x for iso-power is introduced. Modulated by its VCSEL-based optical TX counterpart, the optical RX demonstrates 4x50Gb/s NRZ at 1.5pJ/b with BER<1e-12 and a sensitivity of -6dBm.

Processing for AI

C20.2 A PVT Robust Signed 8-Bit Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications

The frequent data conversion in analog CiM reduces the benefits obtained by analog computing. This paper proposes a signed 8b MAC with hybrid differential capacitor ladders. Then a sparsity-aware DAC and an embedded SAR-ADC are introduced to lower the data conversion overhead. Finally, two activation functions (AFs) are included to further improve efficiency: 1) ReLU is realized by SAR-ADC LSB skipping; 2) tanh is built with analog buffers to bypass data converters.

Power Converters

C21.3 A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control

This paper presents a 5.4V-Vin, 0.6-1.8V Vout, 10MHz LDMOS-based buck IVR chiplet implemented in a 55nm BCD process featuring a self-timed bootstrap technique and same-cycle all-digital ZVS control to achieve 9.3A/mm2 current density and 93.6% peak conversion efficiency, while meeting all reliability constraints. The IVR chip supports a maximum load current of 80A and occupies 8.6mm2 die area.

Security

C13.2 A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS

A fault-injection attack (FIA) resistant AES-256 engine with 100% exploitable fault coverage is fabricated in Intel 4 CMOS. Redundant round computations using isomorphic GF(24)2 composite-field implementations and reconfigurable byte dataflow enable real-time detection of corrupted ciphertexts, while limiting area overhead to 12%. Additive masking circuits with redundant round computations show no side-channel information leakage from 1B traces.

Novel Channel Materials for Advanced CMOS

T3.1 Record Performance in GAA 2D NMOS and PMOS Using Monolayer MoS2 and WSe2 with Scaled Contact and Gate Length

The 2D transition metal dichalcogenides are promising candidates as channel material choice in ultimately scaled CMOS. We report record performance in GAA 2D NMOS transistors using monolayer MoS2 with three advances: scaled gate length (Lg) down to 25nm, scaled contact length (Lc) of 38nm, and the elimination of the low-k “inter-layer” in the gate stack enabling the first fully high-k GAA 2D device. We achieve 90% yield for scaled Lg <50nm with SS of 86mV/dec and on-currents reaching 485μA/μm. Drive currents of 342μA/μm are maintained after contact length scaling down to ~40nm. We report the first BTI on any 2D GAA device and deposited high-k interface, showing HfO2 may be advantageous for 2D reliability compared to typical Al2O3 inter-layers. Signs of short-channel effects are observed at the shortest Lg, identifying EOT scaling as essential area of improvement. We also report record ION=92μA/μm in scaled Lg GAA PMOS transistors with monolayer WSe2.

Emerging Non-Volatile Memories: RRAM, FeRAM, PCM, MRAM-1

T8.5 Reliable Low-Voltage FeRAM Capacitors for High-Speed Dense Embedded Memory in Advanced CMOS

For the first time, anti-ferroelectric (AFE) hafnia-based capacitors compatible to advanced CMOS are demonstrated by (i) bit-line (BL) and plate-line (PL) WRITE (W) voltage scaling down to 1V and 1.3V, respectively, (ii) BL READ (R) voltage scaling down 0.6V, and (iii) robust 10yr reliability at elevated temperature in both fatigue and breakdown, while delivering switching charge for high-speed dense embedded memory. Also, frequency-dependent endurance in ferroelectric (FE) or AFE hafnia is shown to unveil the worst-case scenario for cache-level memory application as well as complex interactions between defects and electric field. Finally, 2.4 to 6.5x cell density over SRAM and sub-100fJ W/R cell energy are projected for embedded FeRAM, showing integrating low-voltage AFE capacitors with advanced logic has great performance potential for next-generation low-power and high-speed dense embedded memory.

About the Author
Scott Bair is a Senior Technical Creative Director for Intel Labs, chartered with growing awareness for Intel’s leading-edge research activities, like AI, Neuromorphic Computing and Quantum Computing. Scott is responsible for driving marketing strategy, messaging, and asset creation for Intel Labs and its joint-research activities. In addition to his work at Intel, he has a passion for audio technology and is an active father of 5 children. Scott has over 23 years of experience in the computing industry bringing new products and technology to market. During his 15 years at Intel, he has worked in a variety of roles from R&D, architecture, strategic planning, product marketing, and technology evangelism. Scott has an undergraduate degree in Electrical and Computer Engineering and a Masters of Business Administration from Brigham Young University.