Intel Demonstrates High Spin Qubit Wafer Fidelity and Uniformity in Single-Electron Control

Samuel Neyens and Otto Zietz are quantum computing research engineers at Intel Foundry Technology Research, where they develop automated measurement and operating procedures for cryogenic wafer probing.

Highlights

• Quantum computing researchers at Intel Foundry Technology Research developed a 300-mm cryogenic probing process to collect high-volume data on the performance of spin qubit devices across full wafers.
• The results demonstrate state-of-the-art uniformity, fidelity, and measurement statistics of spin qubits.
• Researchers also found that single-electron devices from these wafers perform well when operated as spin qubits, achieving 99.9% fidelity for qubits fabricated using CMOS manufacturing.
  
  

Quantum computing researchers at Intel Foundry Technology Research developed a 300-millimeter (mm) cryogenic probing process to collect high-volume data on the performance of spin qubit devices across full wafers, resulting in state-of-the-art uniformity, fidelity, and measurement statistics of spin qubits. Greater uniformity in qubit operation can reduce the control line overhead in larger processors, moving silicon-based quantum computers closer to continued scaling and commercial production. Researchers also found that single-electron devices from these wafers perform well when operated as spin qubits, achieving 99.9% fidelity for qubits fabricated using complementary metal oxide semiconductor (CMOS) manufacturing. The high device yield combined with cryoprober testing provides a straightforward path from device fabrication to the study of spin qubits, eliminating failures due to yield or electrostatics at the dilution refrigerator stage, according to a study published in Nature.

Intel is taking steps toward building fault-tolerant quantum computers by improving three factors: qubit density, reproducibility of uniform qubits, and measurement statistics from high volume testing. First, Intel’s silicon spin qubits are smaller and denser than other qubit types such as superconducting and trapped ion qubits, enabling more spin qubits on a chip. The company’s extreme ultraviolet (EUV) lithography helps achieve this density in combination with high volume on devices. Second, making quantum computers with millions of uniform qubits requires highly reproducible and reliable fabrication. Spin qubits leverage Intel’s 300-mm CMOS manufacturing techniques, which routinely produce billions of transistors per chip. Third, developing large-scale quantum computers in the CMOS manufacturing space requires a high-volume 300-mm cryogenic probing system for fast process iteration and learning. Intel’s entire testing process, from alignment to device measurement, is fully automated and programmable, speeding up device data collection by several orders of magnitude compared with the measurement of singular devices in a cryostat.

The development of full-wafer cryogenic test capabilities enables the optimization of the complex 300-mm fabrication process, which in turn increases device reliability to enable much deeper automated measurements across wafers. In the future, these advances could be used to add more interconnect layers to fabricate 2D arrays with increased qubit count and connectivity, as well as manufacturing high-fidelity two-qubit gates using CMOS industry techniques.

Cryogenic Probing Process

For spin qubits, wafer-scale probing requires further cooling hardware to reach the required temperatures lower than 4 kelvin (K). Developed in collaboration with Intel, the cryogenic wafer prober is manufactured by Bluefors and AEM Afore. The cryoprober can load and cool 300-mm wafers to a base temperature of 1 K at the chuck and an electron temperature of approximately 1.6 K in roughly two hours. After cooldown, thousands of spin qubit arrays and test structures on the wafer are available for measurement.

Figure 1. Process optimization aided by cryoprober feedback. a: Schematic of the gate structure in an optimized spin qubit array. Gates designed to accumulate charge are yellow, blue, and green, while gates designed to deplete charge (screening gates) are red. b,c: Spin qubit device variation and electrostatics performance are improved through optimization of the gate stack.

Spin qubits based on electrons in silicon have shown impressive control fidelities but have historically been challenged by yield and process variation. To achieve high yield, researchers used a combination of processes from industrial transistor manufacturing. The quantum dots are defined by a planar architecture (see Figure 1). Active gates, used for controlled accumulation, are defined in a single layer. In later devices, a second passive layer for screening/depletion is also integrated. The gate electrodes are isolated from the heterostructure by a high-dielectric-constant composite stack (high-K stack) while neighboring gates are isolated by a spacer stack.

To improve device variation and performance, researchers use two approaches – reducing fixed charge in the high-K stack and optimizing the gate layer architecture. Fixed charge in the high-K stack can arise based on the materials and conditions of the deposition, as well as through exposure to subsequent processing. Fixed charge can be reduced in the devices by limiting the temperature of the spacer process to within the typical thermal budget for back-end-of-line (BEOL) processing. These reductions in fixed charge led to reduced crystallization of the high-K stack at lower temperatures. In addition, spin qubit device variation and electrostatics performance are improved through optimization of the gate stack.

After process optimization, researchers characterized the optimized process flow with measurements on 12-quantum-dot (12QD) devices with 60-nanometer (nm) gate pitch. Measurements are fully automated to maximize the speed and consistency of data collection. The 12QD design consists of a linear array of 12 quantum dots with four opposing sensor dots isolated by a center screening gate. The array of 12 quantum dots can be operated as physical qubits in a variety of spin encodings, including single spin qubits (in a 12-qubit array) or exchange-only qubits (in a four-qubit array). Depending on the spin qubit encoding, an optional micromagnet layer can be added to the device and the center screening gate can supply microwave electric fields to control the qubits with electric dipole spin resonance.

As in a CMOS logic process, improving qubit yield is a necessary part of scaling up quantum processors, as larger systems will depend on an increasing number of qubit components to function. To analyze the yield of this fabrication flow, researchers tested 12QD devices across a wafer and calculated component yield for ohmic contacts, gates, quantum dots, and full 12QD devices. This testing method provided fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to low process variation and high yield commensurate with the yield in a leading edge technology node.

High-volume testing with the cryoprober will continue to enable process optimization to reduce variation and disorder, as well as more advanced performance screening (such as charge noise, interdot coupling, and single electron transition disorder) to identify the leading-edge test chips for quantum computing applications. Altogether, these results set a new standard for the scale and reliability of spin qubit devices today, paving the way for much larger and more complex spin qubit arrays of the future.