Vulkan driver - depth target tiling artifacts with mips > 0

[Bright__Jason]

We're hitting some issues with our validation unit tests for Vulkan on intel drivers. Looking for pointers on where our assumptions could be wrong. This works as expected on nVidia and AMD drivers. I hope I can explain it in a sensible fashion....

This test is very simple:

For an image, separate renderpass for each mip level independently.  Clear a fixed color/depth (yellow, plus a non-0 depth value). Then draw a red triangle over half the screen with depth 0. Depth is LOAD_OP_CLEAR and STORE_OP_STORE.

for ( x : mips)
      vkBeginRenderPass - clear depth and color - attachments mip X
      vkCmdDraw() - draw red triangle
      vkEndRenderpass()

Attached files showing RenderDoc capture.

See "mip0.jpg" for correct behavior. Notice the lower right half of the depth attachment is grey. Supplied depth clear value.

For mips NOT zero, we are seeing incorrect behavior.
See mip4_draw.jpg. VkClearDepthStencilValue is 0.75 but the depth has been cleared to 1.0.

Now, if you click on the following vkCmdEndRenderPass you see mip4_ endpass.jpg.

What we see is some sort of tiling - notice the grey bits? They are now the *correct* depth clear value.....? It's like during the store operation, tiles that we touched get the correct depth and the rest are.... wrong. 

Still double checking everything.... hints welcome.