Bay Trail Suspend to DRAM

[BBerg7]

I'm testing S3 (Suspend to DRAM) on Bay Trail E3845 platforms. On Cedarview the DRAM was set to low power self refresh mode by the chipset. How does it work on Bay Trail? The MRC code runs succesfully all the steps for S3, but DRAM does not work.

I think it fails to put the DRAM to low power self refresh mode. The question is how to do that? Are there any documentation or reference code for it?

Best regards,

B-O

[Marcelo_M_Intel]

Hello B-O,

Please go to document # 514148, https://www-ssl.intel.com/content/www/us/en/secure/intelligent-systems/privileged/bay-trail/atom-e3800-m-d-sco-bios-writers-guide-vol2.html?wapkw=514148 Intel® Atom™ Processor E3800-M/D SoC BIOS Writer's Guide, Vol. 2, section

37.2 Memory Space Registers.

In the Table 37-5 you will have Pad Number Mapping According to Pad Name.

Let me know if this is useful to you.

Best regards,

Marcelo

[BBerg7]

Thank you Marcelo!

I will compile the differences for the T-series and I-series. I have postponed the T-series project for the moment, to finish of a customer E3845 project.

Best regards,

B-O