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JTruj2
Beginner
1,445 Views

Baytrail FSP?... post code 0x2a

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Dear embedded communities support group:

I am trying to make a bootloader implementation based on MinnowMax Coreboot firmware; and I am wondering if it is possible to get from you a list of post codes for Baytrail I FSP 1.0.

This will help me much in the debug / development of my own Coreboot bootloader.

I am getting 0x2a post code on port 80

I am using FSP Gold 4 Kit.

My system:

Baytrail I E3845 with 4GB of ECC memory down.

This is our own design and works perfectly with the original AMI BIOS (full functionality).

I already reviewed the full coreboot source code to try to locate the 0x2a post code but I cannot find it, so my guess is this post code could be originated from FSP .

Anybody can help me with this?...... I will be very grateful.

Thank You

JT.

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1 Solution
CarlosAM_INTEL
Moderator
223 Views

Hello, RTS_JT:

Thank you for contacting Intel Embedded Community.

The information that may help you as a reference can be found at the following websites:

https://www.coreboot.org/git-docs/Intel/development.html https://www.coreboot.org/git-docs/Intel/development.html

https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/fsp1_1/cache_as_ram.inc?id=HEAD... l151 https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/fsp1_1/cache_as_ram.inc?id=HEAD... l151

We hope that this information may help you.

Best regards,

Carlos_A.

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5 Replies
CarlosAM_INTEL
Moderator
224 Views

Hello, RTS_JT:

Thank you for contacting Intel Embedded Community.

The information that may help you as a reference can be found at the following websites:

https://www.coreboot.org/git-docs/Intel/development.html https://www.coreboot.org/git-docs/Intel/development.html

https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/fsp1_1/cache_as_ram.inc?id=HEAD... l151 https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/fsp1_1/cache_as_ram.inc?id=HEAD... l151

We hope that this information may help you.

Best regards,

Carlos_A.

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JTruj2
Beginner
223 Views

Thank you again Carlos,

"TempRamInit successful: POST code https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc... l151 0x2A is displayed" <---------- in FSP1.1

But I would like to be sure this also apply for FSP1.0

Anyway this is giving me a trail to follow.

The question again is if:

Anyone here can help me to find additional documented post codes for FSP1.0?

(if there are more).

Have a good day.

JT

CarlosAM_INTEL
Moderator
223 Views

Hello, RTS_JT :

We are glad that the provided information is useful to you.

We suggest you address your Intel(R) Firmware Support Package [Intel(R) FSP] consultations by filling out the https://firmware.intel.com/content/support Intel(R) Architecture Firmware Resource Center Support form.

We hope that this information may help you.

Best regards,

Carlos_A.

MGrai2
Beginner
223 Views

Hey JT.

Maybe Dokument 523922 Intel Atom® Processor E3800 Product Family – Bayley Bay-I Customer Reference Board (CRB) is usefull to you.

Best regards

Michael

JTruj2
Beginner
223 Views

Thank you m.gr

That is the right answer .

With the information you provided I get the following:

P-81 P-80

0x01 0x27 Perform DDR3L Reset

0x02 0x27 Pre Jedec Init

0x03 0x27 Perform Jedec Init

0x01 0x29 Set DDR Initialization Complete (S5 and Fast Boot)

0x01 0x2A Disable BUNIT cache

0x03 0x27 Perform Jedec Init

0x01 0x2D Enable BUNIT cache

0x02 0x2A Search Receive enable Training <---- gets stuck here

It's a bakersport configuration.

I still don't know which is the problem.

I already did many adjustments to BCT and changed microcodes

I am using microcode 901 because I can guess is a D0 stepping processor.

Thank you

JT.

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