E38xx Boot into S4 Issue

[ESmit8]

Hello we've being using the E3827 on our own custom PCB for a while now and are nearly into production stage. We're seeing the following issue on about 10% of our prototype systems:

• The PMIC is providing all A Rails for G3 state. Regulation, noise and sequencing are all okay.
• The Intel's PMC clock is running and PMC_SUSCLK[0] output is at 32.768KHz
• PMIC is waiting for SLP_S4_B to be asserted from the CPU however the CPU does not assert this line and the system is stuck and never goes into S4 state.

The only way we can fix this is to force low the PMC_PWRBTN (J26) signal on the Intel CPU for a second or so. This fix only needs to be done once, after this the intel will boot every time with no intervention.

There is no reference to the PMIC datasheet or the Intel datasheet to the PMC_PWRBTN signal during S4 transition.

Has anyone seen this problem before?

I could apply the above mentioned fix to the production FCT fixture but I would rather find the source of the problem.

Thanks is advance,

Erik

[CarlosAM_INTEL]

Hello, LeicaErik:

Thank you for contacting the Intel Embedded Community.

We suggest you implement the fourth specification change stated on page 38 of the https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/atom-e3800-family-spec-update.pdf Intel Atom(R) Processor E3800 Specification Update document # 329901.

We hope that this information is useful to you.

Best regards,

Carlos_A.

[ESmit8]

Hello Carlos_A,

Thank-you for your reply.

Our PMIC controller does indeed sequence V1P8A before V1P0A. This is as specified (note 5 table 61) of the family datasheet and we have always used this sequencing. Our PMIC controller is BD9596MWV-M from Rohm and this is their preferred sequence.

Unfortunately we are in a mature design phase with product release later this year, we are currently going through EMC compliance testing. Given this sequencing is not "recommended for new designs" is there a recommend work around for old designs? Is my current work around of manipulating the PMC_PWRBTN signal adequate for production? This work around is fixing all effected units but I'm reluctant to commit to this until I'm aware of the root cause of the issue, we can't have units failing in the field due to this problem.

Thanks,

Erik

[CarlosAM_INTEL]

Hello, LeicaErik:

Thanks for your update.

In order to help you, we suggest you address your last consultation by filling out the https://plan.seek.intel.com/us_en_embedded_registration-form-contactsaleswebform_html Intel - Contact Sales form.

We hope that this information may help you.

Best regards,

Carlos_A.