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EMGD - Reasons for LVDS resolution limitation to pixel clock > 20MHz


Hi all,

could anyone explain why the EMGD driver pixel clock must be higher than 20MHz - refer to: http://edc.intel.com/Software/Downloads/EMGD/# faqs http://edc.intel.com/Software/Downloads/EMGD/# faqs ?

We are planning to connect a 4,3" Display which support a maximum resolution of 480x272 and a maximum picel clock of 15MHz and we are concerned about if this is possible.

Thank you

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2 Replies


There are a few reasons there is a 20MHz dot clock lower limit:

1. The LVDS port is designed for more notebook/netbook operation where most will run Windows which has VGA as an absolute resolution lower limit (for startup and emergency modes) but 800 x 600 lowest runtime resolution.

2. The PLL circuit in the chipset was designed to the required range and not lower. It is more expensive and takes more power to have it run over a wider range.

3. The Validation of the chipset is only performed on the POR range which has VGA (20MHz) as the lower limit.

To have the work, you are going to need to:

A. Find a different panel with a higher dot clock,

B. Hope that adding extra long horizontal and vertical sync blanking will allow the dot clock to be set around 20MHz to stay withoin guidelines. Going lower may work for one chip but is likely not to work on another in a different batch.

C. Add extra logic on the LVDS output to allow the LVDS port to be set to 760 x 544 and then throw away the data for every other clock to get down to the resolution you want to try.

I';ve heard that B has worked before, but you need to consult your panel manufacturer to see if that can be worked out.

Hope this helps...

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Thank you Kirk!

Best regards,


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