We are using Intel Atom E3826 in our design. To maintain DDR3 layout guidelines, we need to swap the data bits within the byte lane group. In the E3800 PCB layout guideline document, it is written that DDR3L bit / Byte lane swapping is supported.
Is there any restriction on the swapping of data pins (Ex; DQ0 - DQ7) within byte group?
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The information that may answer your question is stated in section 5.13.2, on page 81 of the Intel(R) Atom(TM) Processor E3800 Product Family Platform Design Guide (PDG) document # 512379. This document can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following website:
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