Intel Atom DDR3 interface bit / Byte lane Swapping?

[RSHAR3]

We are using Intel Atom E3826 in our design. To maintain DDR3 layout guidelines, we need to swap the data bits within the byte lane group. In the E3800 PCB layout guideline document, it is written that DDR3L bit / Byte lane swapping is supported.

Is there any restriction on the swapping of data pins (Ex; DQ0 - DQ7) within byte group?

[David_V_Intel]

Hello RSHAR3, Thank you for posting on the Intel ® communities. I have moved the thread to the appropriate topic. You will be getting a response to your inquiry soon. Regards, David V Intel Customer Support Technician Under Contract to Intel Corporation

[CarlosAM_INTEL]

Hello, @RSHAR3​:

Thank you for contacting Intel Embedded Community.

The information that may answer your question is stated in section 5.13.2, on page 81 of the Intel(R) Atom(TM) Processor E3800 Product Family Platform Design Guide (PDG) document # 512379. This document can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following website:

http://www.intel.com/cd/edesign/library/asmo-na/eng/572379.htm

The RDC Account Support form is the channel to process your account update request. It can be found at:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html

Best regards,

@Mæcenas_INTEL​.