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sbass
Beginner
3,428 Views

braswell sio spi not enabled

Hello,

On braswell, i want use sio spi:

-- My configuration:

Gpio Multiplexing:

179 V14 SPI1_CLK 1 SPI1_CLK V1P8A 0 (20k PU) 0

180 Y13 SPI1_CS0_N 1 SPI1_CS0_N V1P8A 1 (20k PU) 1

181 Y12 SPI1_CS1_N 1 SPI1_CS1_N V1P8A 1 (20k PU) 1

182 V13 SPI1_MISO 1 SPI1_MISO V1P8A Input (20k PU) Input (20k PD)

183 V12 SPI1_MOSI 1 SPI1_MOSI V1P8A 0 (20k PU) 0

I used mode 1.

In device tree of coreboot:

register "lpss_acpi_mode" = "0" device pci 1e.5 on end # 8086 228e - SPI 1 device pci 1e.6 on end # 8086 2290 - SPI 2 device pci 1e.7 on end # 8086 22ac - SPI 3

-- In coreboot trace:

src/soc/intel/braswell/chip.c/enable_dev ( Intel Braswell SoC ), type: 2

vendor: 0xffff. device: 0xffff

class: 0xff Unassigned class

subclass: 0xff ???

prog: 0xff

revision: 0xff

src/soc/intel/braswell/southcluster.c/southcluster_enable_dev ( Intel Braswell SoC )

PCI: Static device PCI: 00:1e.5 not found, disabling it.

-- In kernel:

# lspci -nn

00:00.0 Host bridge [0600]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series SoC Transaction Register [8086:2280] (rev 35)

00:02.0 VGA compatible controller [0300]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Integrated Graphics Controller [8086:22b1] (rev 35)

00:0b.0 Signal processing controller [1180]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series Power Management Controller [8086:22dc] (rev 35)

00:14.0 USB controller [0c03]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series USB xHCI Controller [8086:22b5] (rev 35)

00:18.0 DMA controller [0801]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 DMA Controller [8086:22c0] (rev 35)

00:18.1 Serial bus controller [0c80]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 I2C Controller # 1 [8086:22c1] (rev 35)

00:18.2 Serial bus controller [0c80]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 I2C Controller # 2 [8086:22c2] (rev 35)

00:18.3 Serial bus controller [0c80]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 I2C Controller # 3 [8086:22c3] (rev 35)

00:18.4 Serial bus controller [0c80]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 I2C Controller # 4 [8086:22c4] (rev 35)

00:18.5 Serial bus controller [0c80]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 I2C Controller # 5 [8086:22c5] (rev 35)

00:18.6 Serial bus controller [0c80]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 I2C Controller # 6 [8086:22c6] (rev 35)

00:18.7 Serial bus controller [0c80]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO2 I2C Controller # 7 [8086:22c7] (rev 35)

00:1b.0 Audio device [0403]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series High Definition Audio Controller [8086:2284] (rev 35)

00:1c.0 PCI bridge [0604]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series PCI Express Port # 1 [8086:22c8] (rev 35)

00:1c.1 PCI bridge [0604]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series PCI Express Port # 2 [8086:22ca] (rev 35)

00:1e.0 DMA controller [0801]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO1 DMA Controller [8086:2286] (rev 35)

00:1e.3 Communication controller [0780]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO1 HSUART Controller # 1 [8086:228a] (rev 35)

00:1e.4 Communication controller [0780]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series LPIO1 HSUART Controller # 2 [8086:228c] (rev 35)

00:1f.0 ISA bridge [0601]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series PCU [8086:229c] (rev 35)

00:1f.3 SMBus [0c05]: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx SMBus Controller [8086:2292] (rev 35)

01:00.0 Non-VGA unclassified device [0000]: Altera Corporation Device [1172:e003] (rev 01)

02:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)

In coreboot spi device not found and in kernel, It is the same.

All other device SIO are available, as i2c or hsuart, why spi is disabled ? how to enable spi ?

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5 Replies
CarlosAM_INTEL
Moderator
339 Views

Hello, keziaha:

Thank you for contacting Intel Embedded Community.

It is unclear for us the meaning of the acronym SIO. In case that it refers to Serial IO, we suggest you as a reference verify that your implementation fulfills with requirements stated in the section called Serial IO 2 of the https://mail.coreboot.org/pipermail/coreboot-gerrit/2015-May/026108.html Patch set updated for coreboot: 14ae5d4 DO NOT MERGE: Braswell: Add Braswell SOC support and https://github.com/coreboot/coreboot/blob/master/src/soc/intel/braswell/include/soc/pci_devs.h coreboot/pci_devs.h at master.

It is important to let you know that the coreboot consultations should be addressed as a reference as well at the channels listed in the https://www.coreboot.org/consulting.html coreboot consulting services website.

We hope that this information may help you.

Best regards,

Carlos_A.

sbass
Beginner
339 Views

In document Number: 555139 iotg_brasswell_design

Device and I/O Support Matrix

SIO SPI --> TBD ( for linux/yocto)

TBD is defined now ?

all braswell series support sio spi device ? my reference is N3160 ?

Best regards,

CarlosAM_INTEL
Moderator
339 Views

Hello, keziaha:

Thanks for your reply.

The information that you have mentioned is the latest and apply for all the Braswell devices.

We hope that this information may clarify this situation.

Best regards,

Carlos_A.

sbass
Beginner
339 Views

Hello,

On old generation cpu baytrail: Fsp header file(fspvpd.h) contains :

UINT8 PcdEnableSpi; /* Offset 0x002B */

Not available on braswell, why ?

package fsp for braswell: BSW_FSP_KIT_MR1.tgz provided by intel.

FSP header file is an input for fspsiliconinit(),fspsiliconinit must activate pci device as SPI

Best Regards

Sébastien

CarlosAM_INTEL
Moderator
339 Views

Hello, keziaha:

Thanks for your update.

In order to help you, we will contact you via email.

Best regards,

Carlos_A.

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