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1186GRE UP3 System Memory Interface

ppo
Novice
749 Views

Hello,

We are designing a platform around an Intel TigerLake i7 1186GRE UP3 processor and we would like to enquire about its System Memory Interface, as we have concerns regarding several key points.

  1. General DDR4 and LPDDR memory-down implementation questions:
    1. What are the system memory bandwidth and latency performance trade-offs when using LPDDR4x instead of DDR4?
    2. For a given total system capacity, what are the performance trade-offs between distributing the memories onto both memory controllers, or assigning them to a single controller? For instance, if we want a 16 GB total system capacity, is it better to provide 8 GB to memory controller #1 and 8 GB to memory controller #2, or provide the entire 16 GB to memory controller #1?
    3. What is the burst length supported by the memory controller?
    4. We have encountered rare references to LPDDR5 (for example in document #607872 Table 1). However, our understanding is that there is currently no support for this interface. Can you confirm this?
  2. In-band ECC: the ability to enable in-band ECC is crucial for our application. This feature is listed in the processor's specifications online, but we failed to find a more detailed description in the processor’s documentation.
    1. Can you confirm that the in-band ECC is available for both memory controllers simultaneously? Can it also be enabled only on Memory Controller #0 when #1 isn’t in use?
    2. Is in-band ECC compatible with both DDR4 and LPDDR4x memories?
    3. What is the performance trade-off in terms of storage and system memory bandwidth when using in-band ECC?
    4. In which documentation is the In-Band ECC described?
  3. Memory controller pin timing: can you provide us with information about DDR4/LPDDR4x package pin delays?

For reference, we have already already consulted documents #575681, #575683, #612924 and #607872, but we have been unable to find this information.

Best regards,

Peter

7 Replies
CarlosAM_INTEL
Moderator
708 Views

Hello, @ppo:

 

Thank you for contacting Intel Embedded Community.

 

We received your request but we want to address the following consultation:

 

Could you please let us know the place of purchase of the Intel® Core™ i7-1186GRE Processors related to your request?


We are waiting for your answer.


Best regards,
@CarlosAM_INTEL.

 

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ppo
Novice
671 Views

Hello @CarlosAM_INTEL,

 

Thank you for you reply.

We will purchase the Intel® Core™ i7-1186GRE Processors through EBV Elektronik once our design is sufficiently advanced.

We have exchanged directly with them and we have received a quotation.

 

Best regards,

Peter

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CarlosAM_INTEL
Moderator
647 Views

Hello,  @ppo:

Thanks for your reply.

The information that may help you is accessible when your account is an Intel Developer Zone Premier account. Due to this, you should update it by filling out the form stated on the following website:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Your business email address is needed to avoid any inconvenience. The free email provider's address (such as the one provided by Hotmail, Gmail, Yahoo, or others) is not the proper one for this process. This information and more details can be found on the following website:

https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html

Best regards,

@CarlosAM_INTEL.

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ppo
Novice
622 Views

Hello @CarlosAM_INTEL,

 

Thank you very much for your guidance.

I was able to consult additional documentation through the Premier account access, that allowed me to find some answers.

However, the following points are still unclear to me:

  1. For a given total system capacity, what are the performance trade-offs between distributing the memories onto both memory controllers, or assigning them to a single controller? For instance, if we want a 16 GB total system capacity, is it better to provide 8 GB to memory controller #0 and 8 GB to memory controller #1, or provide the entire 16 GB to memory controller #0?
  2. What is the burst length supported by the memory controllers?
  3. According to the UP3 Design Guide, it is required to include package length in length matching, but I was unable to find the package pin delays for the processor. Could you point me to the document containing this information?

Best regards,

Peter

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CarlosAM_INTEL
Moderator
607 Views

Hello, @ppo:

Thanks for your update.

We have received your last three consultations, but could you please clarify the reasons to request the information that answers them?

We are waiting for your clarification.

Best regards,

@CarlosAM_INTEL.

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ppo
Novice
513 Views

Hello @CarlosAM_INTEL,

The reason for requesting this information is that we are designing a platform around an Intel TigerLake i7 1186GRE UP3 processor (COMe), as mentioned in my original post.

As part of the design process, we need to clarify these points in order to make informed design choices (#1 and #2).

Moreover, point #3 appears essential for proper board layout of the DDR memories.

Best regards,

Peter

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CarlosAM_INTEL
Moderator
463 Views

Hello, @ppo:

Thanks for your update.

We sent an email to the address related to this account with information that may help you to solve this situation.
Best regards,
@CarlosAM_INTEL.

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