About TBT simulation (Burnside Bridge)

[NEC1]

Does Burnside Bridge have a complete IBS file for signal simulation?

The problem is described as follows:

CPU: Tiger-Lake UP3

Re-timer: Burnside Bridge

Sources of ibs files required for Re-timer simulation: Thunderbolt - Burnside Bridge Collateral - Rev 1.65

IBIS model folder:

The pins related to the TBT signal in the .ibs file has a model name of "Analog",

But searching the entire .ibs content only found the model "GPIO":

There seems to be no simulation model available for TBT signal simulation in this Re-timer IBIS model folder.

[CarlosAM_INTEL]

Hello, Eric:

Thank you for contacting Intel Embedded Community.

We sent an email to address related to your community account with information that may help you.

Best regards,

@CarlosAM_INTEL.

[Yangbrian1]

Hello, Carlos 

I also have the same question

Could you share IBIS model information to me ?

Thanks 

Best regards,