Embedded Intel® Core™ Processors
Communicate Intel® Core™ Hardware, Software, Firmware, Graphics Concerns
1213 Discussions

About TBT simulation (Burnside Bridge)

NEC1
Beginner
1,634 Views

Does Burnside Bridge have a complete IBS file for signal simulation?

 

The problem is described as follows:

 

CPU: Tiger-Lake UP3

Re-timer: Burnside Bridge

 

Sources of ibs files required for Re-timer simulation: Thunderbolt - Burnside Bridge Collateral - Rev 1.65

NEC1_0-1614222968140.png

 

 

IBIS model folder:

NEC1_1-1614222968142.png

 

 

The pins related to the TBT signal in the .ibs file has a model name of "Analog",

NEC1_2-1614222968152.png

 

 

 

But searching the entire .ibs content only found the model "GPIO":

NEC1_3-1614222968159.png

 

 

There seems to be no simulation model available for TBT signal simulation in this Re-timer IBIS model folder.

 

 

 

0 Kudos
2 Replies
CarlosAM_INTEL
Moderator
1,614 Views

Hello, Eric:

Thank you for contacting Intel Embedded Community.

We sent an email to address related to your community account with information that may help you.

Best regards,

@CarlosAM_INTEL.

0 Kudos
Yangbrian1
Beginner
1,077 Views

Hello, Carlos 

I also have the same question

Could you share IBIS model information to me ?

Thanks 

 

Best regards,

 

0 Kudos
Reply