The datasheet for the BD82QM77 Platform Controller Hub does not seem to specify whether the DisplayPort main links contain the termination resistors and Tx Vbias implemented on the die. Is this implemented in the physical layer or must the device be terminated externally?
We are investigating a potential level issue with a customer provided UUT (DisplayPort source) that implements the BD82QM77. Per paragraph 3.5.2 of the DisplayPort standard:
a 50 ohm termination resistor is required between Vbias Tx to both the + and - side of each main link. The DisplayPort standard states it "may be integrated on the chip." Does this PCH implement these resistors in the physical layer or must they be implemented externally as discrete components?
Thanks for your clarification.
Based on your last communication, Could you please give all the information related to the proccesor associated to this thread? could you please tell us if the projects related to this forum have been designed by you or by a third-party company? In case that they are third-party units please give the part number, model, name of the manufacturer, where it is stated the information related to it. In case that it is your design, could you please clarify it has been reviewed by Intel and list the sources that you have used to develop it?
We are waiting for your reply.
The hardware in question is GFE (government furnished equipment) that was designed by a third party. The schematic information we have been provided is strictly limited to the DisplayPort interface portion of the hardware and an NDA (non disclosure agreement) prevents disclosure. The issue appears to be level related on the DisplayPort main links. I will disclose that the third party hardware implements external termination resistors on the main links and since most (if not all) of the DisplayPort chipsets I have seen implement the termination/bias on the chip rather than externally, it is suspected this may be the cause.
Can Intel confirm whether the BD82QM77 implements the termination resistors on the DisplayPort physical layer?
This question is directed specifically at the BD82QM77 Platform Controller Hub. I initially searched for PCHs and saw there were several posts to this board so I thought I was in the right location. I now see there is a specific board for PCHs and have posted the question there. I tried to delete this message but the system will not let me. Sorry for the confusion.
Thanks for your reply.
Please let us clarify that some information related to chipsets can be found under the platforms (processors and chipsets configuration) documentation. This is the reason to request the information of the processor associated to the project related to your questions.
Best regards ,
The info that was provided to us ended at the PCH and we have no idea what processor is being used. As a result, my question is targeted at the PCH only.
Thanks for your clarification.
The device mentioned on your communications is part of the Intel(R) 7 Series Chipset family.
Due to this fact, your display port implementations based on the cited device should be based on the information stated in section 3.1, on pages 140 through 177 of the Chief River [Ivy Bridge Mobile Processor and Intel(R) 7 Series Chipset - M Platform Controller Hub (PCH)] Platform Design Guide (PDG) document # 471984 to avoid any inconvenience. This document can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following website:
The RDC Account Support form is the channel to process your account update request or any inconvenience related to the provided website. It can be found at: