Can I implement Memory throttling ( EXTTS# mode ) in Coffee Lake?
It has been connect PCH GPP_0 with SPD EVENT_n. (When DIMM temperature over cirtical temperature , SPD EVENT_n will active Low)
But the result was the same with the EVENT_n deassert condition when I used the memory performance test.
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You should review the information stated in Table 6-13, on page 129 of the 8th and 9th Generation Intel® Core™ Processor Families and Intel® Xeon E Processor Family Coffee Lake and Coffee Lake Refresh External Design Specification Volume 1 of 2 document # 570805, and in sections 7.66 and 7.74, on pages 229 and 236 of the 8th and 9th Generation Intel® Core™ Processor Families and Intel® Xeon E Processor Family Coffee Lake and Coffee Lake Refresh External Design Specification Volume 2 of 2 document # 570806, which may answer your questions. You can find these documents when you are logged into your Resource and Design Center (RDC) privileged account on the following websites:
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