I am working on an Agilex 7 SoC where the SOM HPS DDR clock is preprogrammed. I am attempting to modify the DDR clock in SPL via I²C by reconfiguring the external clock synthesizer before DDR initialization.
The clock update appears successful (verified via probing), but DDR calibration fails afterward and the system does not boot.
Post clock reconfiguration, I observe:
- HMC STAT (0xF80112C0): 0x00000001 (Idle)
- IOPLL remains locked
This suggests the DDR subsystem is not proceeding with initialization after the clock change.
I need clarification on the following:
- Is dynamic modification of the HPS DDR clock in SPL (prior to DDR init) supported on Agilex 7?
- What is the required reset/reinitialization sequence for HMC/DDR after changing the DDR reference clock?
- Does HMC entering the Idle state indicate a missing reset or invalid clock condition?
- Are there any documented constraints or dependencies between the external clock synthesizer and HPS DDR bring-up?
At this point, DDR calibration consistently fails after the clock change, so I’m looking for confirmation on whether this approach is valid and, if so, the correct sequence to make it work.
