As per the 543448-grangeville-pdg-2-2- Document, it recommends separate Debug connector for both the PCH and CPU JTAG connection.
Please clarify whether this is required ? As there is shortage of space in board.
Also let us know whether we can connect both PCH and CPU JTAG in daisy chain configuration. if yes, Is there any order for the same.
we are also trying to implement boundary scan configuration between Xeon D1559 and Intel MAX 10 Series FPGA. also let us know if this is possible.
For the design purpose we are using the below document , please let us know whether any ERRATAS or latest version is available for
Thanks in Advance.
I am going to proceed and move your thread to the Embedded Xeon® Community, so you can get recommendations from fellow community members.
Intel Customer Support Technician
A Contingent Worker at Intel
Thank you for contacting Intel Embedded Community.
The information stated in documentation has been tested and validated by Intel for the device related to it.
Due to this fact, the configuration and information stated in section 19, on pages 399 through 426 of the Grangeville with Intel Xeon Processor D 1500 Product Family Platform Design Guide (PDG) document # 543448 [Revision: 2.2, September 2017] and section 3 pages 41 through 44 of the Grangeville Platform Design Checklist document # 570322 [Revision: 1.1, November 2016] that you have mentioned is the recommended.
However, feel free to implement your desire configuration but it should be tested and validated on your own.
The notes 9 and 10 of Table 19-3, and notes 7 and 8 of Table 19-7 on pages 408 and 417 of the cited PDG has information that may help with your FPGA implementation.
The documents listed on this communication are the latest available. You can confirm this information at the following website: