How to "enable / disable" ECC checking on Xeon 5520?

[栋阎]

Hi:

My main problem is "How to enabling and disabling ECC checking on Xeon E5520?". Here is my platform information：

Motherboard : ASUS Z8NA-D6

Chipset : Intel 5500 I/O Hub (rev 13)

Processor : Xeon E5520

Memory : Kingston 4G DDR3 1600 ECC(KVR16E11/4)

According to the datasheet of Xeon E5520, enabling and disabling ECC checking can be done by set a register named "MC_CONTROL". But whether read or write that register, value read from that register is ZERO. First I ask for help to the communities (http://communities.intel.com/thread/33885 http://communities.intel.com/thread/33885, sadly, nobody answer me till now.), then I ask through Intel contract support. They said it was cased by my motherboard(ASUS Z8NA-D6), because it doesn't support manipulate that register "MC_CONTROL", but they are not sure If Intel's server board will support this function. So my contract support suggest me to ask for help in this communities.

My question is "Which motherboard (no matter provide by intel or third party) can support dynamically enabling and disabling ECC checking of main memory?". If it is necessary, I will buy new processor and motherboard to meet this requirement. Please recommend me a configuration which can satisfy this.

A previous research paper based on ECC checking was published on HPCA05. This paper using Intel E7500 chipset to dynamically enabling and disabling ECC checking by OS. Which can be found here http://opera.ucsd.edu/paper/HPCA05-SafeMem.pdf http://opera.ucsd.edu/paper/HPCA05-SafeMem.pdf

Here is my code, try to enabling and disabling ECC checking. This code segment was insert into Linux kernel function "start_kernel()", immediately before calling of "rest_init()", start_kernel() defined in 2.6.37/init/main.c。

>>>

unsigned int mc_status_data = 0;

unsigned int bus = 0, slot = 3, func = 0;

unsigned int base = 0x80000000 | (bus << 16) | (slot << 11) | (func << 8);

unsigned int mc_control_offset = 0x48;

unsigned int mc_status_offset = 0x4c;

outl_p(base | mc_status_offset, 0xcf8);

mc_status_data = inl_p(0xcfc);

printk(KERN_ALERT "0. mc_status_data: %08x\n", mc_status_data);

outl_p(base | mc_control_offset, 0xcf8);

unsigned int mc = inl_p(0xcfc);

printk(KERN_ALERT " mc_constrol_data : %08x\n", mc);

outl_p(mc | 2, 0xcfc);

mc = inl_p(0xcfc);

printk(KERN_ALERT " mc_constrol_data : %08x\n", mc);

outl_p(base | mc_status_offset, 0xcf8);

mc_status_data = inl_p(0xcfc);

printk(KERN_ALERT "1. mc_status_data : %08x\n", mc_status_data);

outl_p(base | mc_control_offset, 0xcf8);

mc = inl_p(0xcfc);

printk(KERN_ALERT " mc_constrol_data : %08x\n", mc);

outl_p(mc & 0xfffffffd, 0xcfc);

mc = inl_p(0xcfc);

printk(KERN_ALERT " mc_constrol_data : %08x\n", mc);

outl_p(base | mc_status_offset, 0xcf8);

mc_status_data = inl_p(0xcfc);

printk(KERN_ALERT "2. mc_status_data : %08x\n", mc_status_data);

while(1);

<<<

I had running this code on my platform, all register value showed by printk was zero.

Thanks a lot.

Dong Yan