The Processor D-1559 power rails ( PVCCIN , PDDQ,P1V05 ) are required for SVID control or any exemptions is there for particular power rail.

[SergioS_Intel]

Hello Kumaran,

I am going to proceed and move your thread to the Embedded Community and an Intel dedicated team will continue further assisting you.

Best regards,

Sergio S.

Intel Customer Support Technician

A Contingent Worker at Intel

[CarlosAM_INTEL]

Hello, @KMANO3​:

Thank you for contacting Intel Embedded Community.

The information that may answer your questions can be found in sections 18.2.9, 5.5.2, 18.4.1, 18.6, 18.2.4, 18.2.11, and 18.3.1; also Tables 18-26, 18-30, 18-31 and 18-32; on pages 127, 352, 353, 356, 357, 359, 360, 362 through 366, 368, 372 through 374 of the Grangeville with Intel(R) Xeon(R) Processor D-1500 Product Family Platform Design Guide (PDG) [Revision 2.2, September 2017] document # 543438 This document can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following websites:

http://www.intel.com/cd/edesign/library/asmo-na/eng/543438.htm 

The RDC Account Support form is the channel to process your account update request and any inconvenience related to the cited sites. It can be found at:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html

Best regards,

@Mæcenas_INTEL​.