[I210-IT] schematic design - JTAG_CLK pullup or pulldown ?

[Tang_Hongbo]

Hello Support Team,

    I am desgining a product with I210-IT.  I wonder to know how to treat the JTAG_CLK pin if JTAG interface is not used.  in I210 datasheet ver 3.7 Table 14-1, it is said Signal should be connected to ground through a 3.3 KΩ pull-down resistor, but in checklist ver 2.7, it is said Pins JTAG_TDI(29), JTAG_CLK(19) and JTAG_TMS(18) should be pulled high with 3.3K Ω resistor value.  

    I am confused. Which is correct if JTAG interface not used ?

    Can you help me ?

[Pintu]

Hi Tang_Hongbo,

Greetings for the day!

As per this case concern, for this design case, kindly reach out to the embedded community. If you have any additional concerns, please do not hesitate to contact us.

Please find below the link to reach the embedded community:

https://community.intel.com/t5/Embedded-Products/ct-p/embedded-products

Thank you for using Intel products and services.

Regards,

Manoranjan

[Pintu]

Hello Tang_Hongbo,

Greetings for the day! 

I hope this message finds you well.

We are following up to find out if you were able to find the information we provided. 

Kindly reply back to confirm and let us know if you need any further assistance.

Thank you for using Intel products and services.

Regards,

Manoranjan Das

Intel customer support.

[Tang_Hongbo]

Hello Manoranjan,

   Greetings for the day! 

   I haven't got the answer to this question. Can you help to check ?

Best Regard,

Hongbo

[Hayat]

Hello Tang_Hongbo,

Since this issue is related to the FPGA, we request you to post your question or issue to below link:

https://community.intel.com/t5/FPGA/ct-p/fpga

Our dedicated team will assist you further.

Thus, we will proceed to close the thread here.

Feel free to reach out to us if you need further assistance.

Regards,

Hayat_Intel