FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Beacon signal for lowest power mode in PHY IP core

Honored Contributor II


Currently I works with PHY IP core with PCI Express, in that I had problem related to Beacon signal, I have no any idea about Beacon signal used in lowest power mode P2 in PCI Express, I don't know the pattern of Beacon signal and also not found any declaration about how to transmit this and detect this signal, If any one have any idea about that then please share it with me. 

I attached one document for pipe interface description.
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