I'm trying to connect a sensor to EP4CE40F23C7 Cyclone IV E FPGA.
It's supposed to be connected to a bidirectional LVDS drivers, I did the proof of concept with a board with such drivers and it works.
I would like to achieve the same thing without the middle board. The board supporting the FPGA have some FPGA pins directly connected to 2.54mm header pin, including U9 (IO DIFFIO_B13p) and V8 (IO DIFFIO_B13n). I intanciated the buffer_lvds_bidir via the Quartus wizzard and connected as follows :
inst_buffer_lvds_bidir : buffer_lvds_bidir port map( datain => sl_DATA_DV_j404, dataio => io_sensor_data_p, dataio_b => io_sensor_data_n, dataout => sl_DATA_RC_j404, oe => sl_DE_j404, oe_b => not(sl_DE_j404) );
Here is the *.qsf extract :
set_location_assignment PIN_V8 -to sensor_data_n
set_location_assignment PIN_U9 -to sensor_data_p
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sensor_data_p
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sensor_data_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sensor_data_p
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sensor_data_n
set_instance_assignment -name SLEW_RATE 2 -to sensor_data_n
set_instance_assignment -name SLEW_RATE 2 -to sensor_data_p
And what I get stopping Fitter step :
Error (176172): Can't place node "sensor_data_p" -- node is a differential I/O node
Error (171000): Can't fit design in device
Could you please guide me to what is the matter ?
- FPGA Design Tools
The pin assignment concerning the bidirectional LVDS signal is given in the form of the *.qsf extract. If a larger view of the design is needed, I may need to do some proofing beforehand.
Thinking about it, it appears to me that it doesn't do much sense to do LVDS with 3.3V IOs. Am I wrong ?