Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

[Zarquin]

Dear community,

is it possible to establish an Ethernet connection from Cyclone V Dev Kit to my 100Mbps LAN PC? And if so, what configuration is necessary?

On the FPGA, a Triple Speed Ethernet IP MAC is connected via RGMII to the Marvell 88E1111 PHY on the board.

I have configured the MAC and PHY registers.
MAC Cmd Config: 0x2033 (SW Reset, Pad en, RX en, TX en)
Marvell Ctrl Reg: 0x9140 (SW Reset, 1000 Mbps, Full Duplex)

Do I need to explicitly configure the Marvell Ctrl Register to 100Mbps to establish a 100Mbps connection to my PC or does the PHY do this automatically?

The Marvell has the hardware configuration:

config 0, config 1, config 3 = 000 (PHY Address = 00000, Disable 125MHz clock)

config 2, config 5 = 111 (ANEG =1110 = Auto-Neg, advertise all capabilities, prefer Master)

config 4 = 011 (HWCFG = 1011 = RGMII to copper)

config 6 = 010

[FvM]

Hi,
unless you force a PHY to 1GBPS only, it will autonegotiate the highest available speed with the peer, in this case 100 MBPS. There are a few cases where autonegotiation may fail, e.g. the peer advertizes 100 MBPS but the cable is too bad.

[Zarquin]

Hi FvM,

thank you very much for the answer.

Do I have to adjust the tx_clock to the autonegotiated speed in the PHY?

More precisely: Do I have to query the speed from the corresponding Marvell PHY register and adjust the tx_clock frequency generated by the FPGA to the actual speed? Or can the tx_clock continue to operate at 125MHz ?

[FvM]

Hi,
yes, RGMII reference clocks and data rate change according to 10/100/1000 ethernet speed.

[FvM · Accepted solution]

Hi,
RGMII reference clocks and data rate changes with ethernet speed and has to switched in MAC. Reading negotiated speed through MI is the usual way to handle it.

[Zarquin]

Hello FvM,

I see.

Any idea from which Marvell 88E1111 PHY register I can read the current ethernet speed? I tried register 4_1.11:10, but that was apparently wrong.  Now I am at a loss.

[FvM]

Hi,
unfortunately I don't have 88E1111 documentation at hand. Sorry.

[Zarquin]

OK I have found it. Seems to be register 17 (below). And apparently the connection does have 1000Mbps. Because the read register 17 shows: 0xAC00

So far, everything seems to be right.
But now I'm really wondering why I can still only receive packets but not send any packets, even though all TX Avalon-ST signals are set correctly in Signal Tap II?
I am testing with Wireshark. Nothing is coming in and the TX LED on the board is not lit either. Only the RX LED flashes.

I read about timing issues. https://ethernetfmc.com/docs/user-guide/rgmii-timing/ 

But can this really be the reason why nothing is sent at all?

[Zarquin]

Hi FvM,

my initial question has been answered.
I will start a new thread for the TX problem
Thanks a lot!

[Paveetirra_Srie]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread. 

Thank you.