FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6352 Discussions

DDR3 Controller with UniPhy User Interface Issue for Stratix V

Altera_Forum
Honored Contributor II
808 Views

Hi all, 

I have been using bitware s5ph-q board which has on-board 2 banks of ddr3 ram, each of 4GB. I need to test the memory so that I can use it for my project.  

In DDR3 controller with uniphy parameter window, I set row width to 16, column width to 10, bank width to 3 and interface width to 64 which maps to 4GB according to formula provided in altera knowledge base. 

http://www.altera.com/support/kdb/solutions/rd01202012_132.html 

But when I generated my Qsys project, the user interface which is an avalon-mm slave interface had address width of 26 bits and writedata and readdata of 512 bits. 

In general we know that, to access 4GB we need 32-bit address. But I can't able to understand how DDR3 controller is managing it by 26 bits. 

And also observed that the writedata and readdata are dependent on the interface width parameter, being multiple of 8 (in this case 64*8=512). 

 

So I have a confusion of how to provide data to the controller so that I can have access to complete 4GB. 

 

Is anyone here has a proper explanation? 

 

Thanks in advance :)
0 Kudos
0 Replies
Reply