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Error while adding the DDR Example design to top file : Error(21794): Quartus Prime Full Compilation

ArjunTechM
Beginner
120 Views

Am planning to use example design of DDR4 in one of my application project.

But while integrating this DDR4 Example design as a component on Agilex FPGA: AGIB027R31B2E2VAA with their corresponding IO Pins. am facing the below error(21794).

Please find the working code attached and please help me to clarify this issue as early as possible.

 

 

Error while adding the DDR Example design to top file : Error(21794): Quartus Prime Full Compilation was unsuccessful.

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4 Replies
AdzimZM_Intel
Employee
87 Views

Hi ArjunTechM,


Which compilation stage that this error occurred?


If possible, may I know on how the error can be replicated?

Are you already attached the code? Because I cannot see it in this thread.


Regards,

Adzim


ArjunTechM
Beginner
78 Views

Hi Adzim,

Could you note, I get this error while running the stage of Analysis and Synthesis.

Please find the code attached.

Please help me to resolve this issue.

 

Thanks,

Arjun 

 

 

AdzimZM_Intel
Employee
59 Views

Hi Arjun,


Thank you for sharing your feedback and the code.


I will try to replicate the issue from my side and check the design.


Regards,

Adzim


AdzimZM_Intel
Employee
50 Views

Hi Arjun,


I have checked your design that you have attached.

I cannot reproduce the error that you have stated in previous comment but can see other error.


In this design, the alert pin is set to output port which is causing the error.

Change the alert pin port to input will resolve the error.

The change can be made in top level file at line 159.

Then you should be able to compile the design.


Please let me know if the issue still not resolve.


Regards,

Adzim


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