FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6369 Discussions

Filter output value is lower than expected

Altera_Forum
Honored Contributor II
899 Views

Hi, 

 

I have a fir compiler with the following settings: 

 

Input Bit Width: 16 

Coefficient Scaling: Auto with 16 Bits 

Filter Type: LP with 37 Coefficients 

Sample Rate: 50 MHz 

Cut Off Frequency: 10 MHz 

Passband Ripple: near 0 dB 

 

A NCO core with a 16 Bit output supplies the filter with a 1 MHz sinus signal. I analyzed the full resolution output (38 Bits) of the filter in Signal Tap II. 6 MSB Bits were identical so I truncated 5 MSB Bits. I also truncated 17 LSB Bits to get 16 Bits output.  

But the filter outputs a sinus signal that is attenuated by about -4 dB. 

In the Frequency Response Tab in fir compiler parameterize GUI it should be near 0 dB. 

Does anyone have an Idea what the problem could be?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
210 Views

since you are truncating 17 bits,in effect you are dividing the sum of internal products by 2^17. Thus if you scale your coeffs as: 

 

coeff = coeff/sum(coeff) *2^17 then you should get unity dc gain. but what actually happens at 1MHz may be due to your response
0 Kudos
Altera_Forum
Honored Contributor II
210 Views

thanks kaz! I scaled the coefficients as you said and now I get the right output signal.

0 Kudos
Reply