How is PCIe coreclkout_hip generated?

[corestar]

I'm using a Cyclone V GT PCIe Avalon ST core. It might be helpful to use coreclkout_hip to run our application layer, but it is not clear how that clock is generated and how much jitter it has.

I had assumed this clock was generated from the 100 MHz refclk. But in spread spectrum mode, the default (to reduce EMI) on the processor we are using, the refclk can have enormous jitter. I assume the hard IP deals with the on the Phy side, but if coreclkout_hip is generated from refclk, does it clean the jitter?

But looking at Figure 6-4 in the "Cyclone V Avalon ST User Guide", it shows:

It looks like refclk and coreclkout_hip are not related. I realize this is just a block diagram, but if coreclkout_hip is not generated from refclk, how is it generated? I there a clock source in the PCIe hard IP?

And much  jitter does it have?

[wchiah]

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate and get back to you soon. Thanks for your patience.

Best regards,

Wincent_Intel

[wchiah]

Hi,

Yes you are correct, the coreclkout_hip source is from PCIe HIP.
if you are referring to PCIe Protocal Jitter specification, total Jitter for 

1. Pcie cable - 100 ps
2. PCie gen1 - 100 ps
3. Pcie gen2 - 50 ps

Detail information about the jitter spec, you may get from Cyclone V Characterization Report.
But I don't think you can obtain the report from public release platform.
IF you have access to Intel Premium Support (IPS) you may file an ticket to get it as well or You may contact your Intel Distributor as alternative.

Regards,

Wincent_Intel

[corestar]

Hello,

---

Yes you are correct, the coreclkout_hip source is from PCIe HIP.

Are you saying the PCIe HIP has a clock generator independent of incoming PCIe refclk?

Are there any specs on it's jitter and accuracy? I'm thinking of using it instead of an external clock.

I'm familiar with the PCIe jitter specs, but if the coreclockout_hip is generated from refclk, I was wondering about the situation where PCIe Spread Spectrum is enabled (the norm on many systems) as described here:

PCIe Spread Spectrum Clocking 

In this case, refclk is modulated with a 35 KHz triangle wave and the incoming PCIe refclk itself has very high jitter. Apparently has high as 4ns. This is on purpose to reduce EMI.

The PCIe IP itself is designed to handle it, but other parts of a system are not and depend on low jitter.

Thanks

[wchiah]

Hi,

Based on my understand via PCIe Specification, please correct me if you feel I am wrong

1. Refclk (Reference Clock): This is typically provided externally to the FPGA and is used by the PHY to synchronize the transmission and reception of data. In spread spectrum mode, as you mentioned, the frequency of this clock is modulated slightly to reduce electromagnetic interference (EMI). The amount of jitter on this clock can indeed be significant, especially in spread spectrum mode.

2. Coreclkout (Core Clock Output): This clock is generated by the FPGA's hard IP, usually from a stable internal reference clock source. It's typically used to clock the internal logic of the FPGA design, including any user logic interfacing with the PCIe core.

Not sure this able to help you or not, let me know if you have any other question.

Regards,
Wincent_Intel

[corestar]

@wchiah 

Thanks for the info.

If they can really generate a stable low jitter clock inside the FPGA, it would be really useful to make that available independent of the PCIe core. 

For now, I think the safest route is to just use an external clock source to drive most of the FPGA logic and coreclockout_hip for the PCIe. Lots of clock domain crossings but so be it.

Thanks,
Dave

[wchiah]

Hi Corestar,

Glad that my suggestion able to help you to move forward.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[corestar]

Hello,

It's still not very clear how all this works, but apparently the information, such as jitter and accuracy of coreclock, is not available for some reason.

Please go ahead and close the ticket.

Just as a side note, Timing Analyzer does in fact report coreclockout as a separate clock to the incoming PCIe_ref clock pin (as opposed to one generated by it).

[wchiah]

Hi

Thanks for your confirmation to close this loop, Glad that you are able to proceed further.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.