Intel Opencl FPGA blocking channel

[ADua0]

For Opencl FPGA blocking channel , if there are two independent read/write channel operation, are they actually happening in parallel. In the system viewer of report it appears there are no dependencies so I believe they should happen in parallel but how do you verify?

In code sample below what should happen is that b1 and a should happen in parallel with b2 and a2. 

Here is example code,

int b1= read_channel_intel(c1);

int b2 = read_channel_intel(c2);

a = b1 *100 ;

a2 = b2 * 200;

write_channel_intel(c1,a);

write_channel_intel(c2,a2);

[HRZ · Accepted solution]

No, independent channel operations happen sequentially and at an order decided by the compiler. This is why mem_fence(CLK_CHANNEL_MEM_FENCE) is provided to avoid potential deadlocks resulting from channel operation re-ordering by the compiler. In your example it is very much possible that the channel operations might result in a deadlock if they are re-ordered by the compiler. You should make sure to use a mem_fence(CLK_CHANNEL_MEM_FENCE) both between the two channel read operations and the two channel write operations to avoid this.

[ADua0]

Okay, so would you recommend adding this memory fence for all the channels I have in my design ?

[HRZ]

Certainly not; if a certain channel order is required to avoid deadlocks, then you should use a mem_fence to enforce the ordering. If not (i.e. channel operations can be safely re-ordered), then let the compiler decide the order of the operations.

[ADua0]

By deadlock you meant which channel operations are stalling maximum amount of time?