PCI Express translation

Altera_Forum · ‎11-06-2007

Hello,

I have a problem to understand how you calculate the DLLPs CRC in the Altera PCI Express Megacore function. I ran the testbench generated and I took the first 4 bytes of some DLLPs and I applied the 16bits CRC algorithm based on 0x100B polynom with an initial value of 0xFFFF. And I didn't generate the proper result with any DLLPs. Need I to descramble them to do it properly or not? It's with the XIO1100 PHY. Could you help me with that?

Secondly, why do I receive, with this PHY, the logical idle scrambled ? Normally it should be unscrambled by the PHY before provided to my Cyclone II FPGA ?

Thank you very much for your support.

Altera_Forum · ‎11-10-2007

Yes you have to unscramble the data before checking the DLLP CRC. Scrambling is a Physical Layer function. CRC is a Data Link Layer function. Likewise when transmitting you have to generate the CRC first and then scramble the data.

Data from the PHY is still scrambled because that is the way the PIPE interface specification specifies it to be done.

Altera_Forum · ‎11-11-2007

Thank you for your answer.

The thing is, that normally my XIO1100 PHY should scramble the data for me. It is written in the XIO1100 documentation. Actually it seems that it isn't the case.

So I guess that the XIO1100 simply doesn't make any scrambling function ?

Thanks for details ;)

Marc

Altera_Forum · ‎11-12-2007

I see that the XIO1100 datasheet makes one reference to scrambling/unscrambling in the beginning and then makes no further reference to scrambling. The Altera PCIe core definitely does the scrambling/unscrambling functions internally when using the XIO1100, so I think that must be an incorrect statement in the XIO1100 datasheet.

Altera_Forum · ‎11-13-2007

Yeah I think so too, it's very disappinting from TI because I lost many hours investigating after this problem... So thank you very much ;)

Marc