FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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block are vacant in the ip core of PCIe.

Altera_Forum
Honored Contributor II
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file:///C:/DOCUME%7E1/RAJESH%7E1.KUM/LOCALS%7E1/Temp/moz-screenshot.png file:///C:/DOCUME%7E1/RAJESH%7E1.KUM/LOCALS%7E1/Temp/moz-screenshot-1.png in the Architecture of the Transaction Layer: Dedicated Receive Buffer per Virtual Channel page no 76, 

there are many block left black .. can u please help me what is it ..!:(

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Altera_Forum
Honored Contributor II
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plz get me back soon

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Abe
Valued Contributor II
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Since the Data and Descriptor are inputs to this block, its most likely a buffer / FIFO that stores both. Data & descriptors are for the SGDMA IP that the PCIe uses. When starting a PCIe transaction, the command and data have to be fetched from memory using the descriptor that is stored in the buffer. The software application controls the DMA, programs the descriptors and starts/stops the data transfer to the PCIe IP.

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