running AN708 on Quartus 17.0

[dsun01]

Dear Intel Support/Expert, 

I am learning PCIe access DDR memory. the AN708 is a good example, I installed Quartus 17.0, and everything seemed very smooth. except the Simulation stopped due to Fatal error!

I downloaded the AN708_q170 from Intel. use quartus 17.0 open the top.qsys. generate testbench system and run the simulation. 

how to fix this "# FATAL: 175149 ns LTSSM does not change from DETECT.QUIET"?

is there a document that described LTSSM?

Thank you,

David

# INFO: 952 ns Completed initial configuration of Root Port.
# INFO: 4205 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 5309 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 18173 ns RP LTSSM State: DETECT.QUIET
# INFO: 18509 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 19549 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 32413 ns RP LTSSM State: DETECT.QUIET
# INFO: 32749 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 33789 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 46653 ns RP LTSSM State: DETECT.QUIET
# INFO: 46989 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 48029 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 60893 ns RP LTSSM State: DETECT.QUIET
# INFO: 61229 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 62269 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 75133 ns RP LTSSM State: DETECT.QUIET
# INFO: 75469 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 76509 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 89373 ns RP LTSSM State: DETECT.QUIET
# INFO: 89709 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 90749 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 103613 ns RP LTSSM State: DETECT.QUIET
# INFO: 103949 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 104989 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 117853 ns RP LTSSM State: DETECT.QUIET
# INFO: 118189 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 119229 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 132093 ns RP LTSSM State: DETECT.QUIET
# INFO: 132429 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 133469 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 146333 ns RP LTSSM State: DETECT.QUIET
# INFO: 146669 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 147709 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 160573 ns RP LTSSM State: DETECT.QUIET
# INFO: 160909 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 161949 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 174813 ns RP LTSSM State: DETECT.QUIET
# INFO: 175149 ns RP LTSSM State: DETECT.ACTIVE
# FATAL: 175149 ns LTSSM does not change from DETECT.QUIET
# FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation stopped due to error!
# ** Note: $stop : ./../../../ip/top_tb/DUT_pcie_tb_ip/altera_pcie_a10_tbed_170/sim/altpcietb_ltssm_mon.v(157)
# Time: 175149 ns Iteration: 1 Instance: /top_tb/dut_pcie_tb/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/ltssm_mon
# Break in Function ebfm_log_stop_sim at ./../../../ip/top_tb/DUT_pcie_tb_ip/altera_pcie_a10_tbed_170/sim/altpcietb_ltssm_mon.v line 157

[dsun01]

More details. 

from PCIe_Link_Training_FTA_2p0 

while I run the simulation, 

the host bfm side rp_ltssm loop 0, 1, 2. the dut side ltssstate was always 0. 

currentspeed was always 0, lane_act always 0

on the top level of testbench, there is a module 

top_inst_dut_npor_bfm_ip top_inst_dut_npor_bfm (
.sig_npor (top_inst_dut_npor_bfm_conduit_npor), // conduit.npor
.sig_pin_perst (top_inst_dut_npor_bfm_conduit_pin_perst) // .pin_perst
);

these two outputs are always StX. and they feed into the  npor and pin_perst of the DUT. 

I guess here is the problem. this module was generated by the platform designer. 

if this was the problem, please give me some suggestion how to fix this problem.

Thanks,

David 

[dsun01]

I attached archived project here. 

The LTSSM toggling on the BFM side 

# INFO: 161949 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 174813 ns RP LTSSM State: DETECT.QUIET
# INFO: 175149 ns RP LTSSM State: DETECT.ACTIVE
# FATAL: 175149 ns LTSSM does not change from DETECT.QUIET

but on the DUT side. LTSSM was always 0. 

[wchiah]

Hi David,

Nice to see you back. Thanks for such detail sharing.

Mind me to ask do you just purely run in simulation ? or there is any hardware connected on it ?

There is few reason why this happen

1. Simulation time is not long enough to reach the simulation end.

2. This demo project is for hardware test rather than simulation test.

Could you please confirm back in this ?

Regards,

Wincent_Intel

[dsun01]

Hi Wchiah, 

There is not any hardware, It purely Intel package, extract by Quartus 17.0.0.290. use platform designer open the .qsys and update the out-of-date IP.  use the ModelSim - INTEL FPGA STARTER EDITION 10.5c, run the simulation. 

it is not the run time problem, it is the PCIe link training no response from the DUT. 

I guess the problem is this module, the output of this module 

npor and pin_perst will be feed into the DUT, both of them are X. 

top_inst_dut_npor_bfm_ip top_inst_dut_npor_bfm (
.sig_npor (top_inst_dut_npor_bfm_conduit_npor), // conduit.npor
.sig_pin_perst (top_inst_dut_npor_bfm_conduit_pin_perst) // .pin_perst
);

Thank you,

David

[dsun01]

Hi Wchiah, 

Can I assume that your second statement means the simulation environment provided by the Intel development environment is not guaranteed working. 

2. This demo project is for hardware test rather than simulation test.

as a learner, environment can access more detail of the core, it is easier to use than the signal tap.

Thank you,

David

[wchiah · Accepted solution]

Hi David,

My apologies for late reply as my time is quite occupied these few days.

Thanks for your patience and the follow-up question.

Yes, the design is for hardware test rather than simulation test as mention in the user guide.

If you want to run the simulation, my suggestion is you can try to refer to the Arria 10 User guide

under section 2.1. Directory Structure and 2.4. Simulating the Design

Let me know if there is anything else that I can help you.

Regards,

Wincent_Intel

[dsun01]

Wchiah, 

So, the demo is just show that Intel's core works. which nobody should doubt about.  I will follow the Intel's idea, load the code to the board and use signal tap to track how the signals toggling. 

thank you for the suggestion. 

David 

[wchiah]

Hi David,

I understand your feeling,  you are free to doubt how it works.
But I just share some of my personal thought about this issue on this specific for this design example ONLY,
As you know sometimes there is an incident that happens as the simulation result is not the same as the hardware.

There are multiple issues causing that to happen, for example, clock frequency on the board, Using delays in test bench design, timing checker wasn’t given the right clock rate, and other related reasons. To be honest, I do not have had a chance to go deeply into this design example and find out why the architecture is preferred to work well only in hardware instead of simulation yet at the moment, but I do understand it is to provide the most accurate test experience/result to the user specific to this design example . 

If you need to simulate it, the simulation environment is provided Arria 10 User guide that is tested.

Apologies for any inconvenience caused to you.

Regards,

Wincent - Personal thought

[dsun01]

if the auto created simulation environment doesn't work, it will be great to explicitly claim that in the AN708 to save some time for learner like me. 

some designers like me always think Intel as a gold model. we will feel disappointed for any Non perfection. it is not Intel's problem at all. 

Thank you,

David

[wchiah]

Hi David,

I understand how you feel, I feel apologize for that. 
As mentioned, there are multiple reasons why it is set to limit to hardware test. 
(as FPGA could be very complicated sometime/somewhere)

But I believe, it is to provide customers with the most accurate test experience.

The requirement of running the reference design is stated in the AN708 user guide, page 10

I really apologize for any inconvenience caused to you.
For this case, my best help to you will be submit an internal ticket to request a simulation environment for AN708 design.
So that the designer know there is a need for this. Hope this helpful to you.

Regards,

Wincent_Intel

[wchiah]

Hi David,

Again, I do apologies for any inconvenience caused to you. If there is no further question on this case I will set this as close.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Happy to work with you on a few previous cases and now, hoping to hear back from you in the future.

Regards,

Wincent_Intel

[dsun01]

please close this thread.