The design requires accessing DDR through 2 channels using seperate DIMM.
The target device is Arria 10.
Do you mean dual rank, like separate chip selects? Are you referring to a particular development kit or your own board? If it's your own board, are you saying you want to access two separate DIMMs?
Also, from which documentation you notice dual channel? I don't think Intel FPGA EMIF claim about "dual channel" term anywhere. And what sstrell asking is correct. Are you mean dual rank? or may you are asking 2 DDR4 interface which require you to instantiate the IP 2 times from your top level. when there are dual DIMM, there are few possibility like single dual DIMM interface, 2 interface with 2 DIMMs.
Thanks for the reply!
The precise term mentioned is "dual slot interface" in arria 10 EMIF user guide
1. What the design requires is having two different interfaces to access ddr simultaneously. As mentioned in your reply, is it possible to have two memory controller IP's instantiated in the top level?
2. And when there are two DIMMS of 4GB each, which makes up for a toatal memory of 8GB, each interface (in case two memory controllers are used) can access entire 8GB memory?
3. Also, could you please let me know what single dual DIMM interface (mentioned in your reply) is?
Dual slot interface is referring to 2 separate DIMM slots (the table on page 227 of the guide you linked). The user guide is saying that with a single instance of the EMIF IP, you can control up to 4 ranks, meaning you can have up to 4 CS signals. A DIMM in a single slot may have 1, 2, or 4 ranks, whereas with dual slots, you could have 2 DIMMs, each with 2 ranks (2 CS signals for each DIMM), both controlled by a single instance of the IP.
1) Yes, you can have more than one memory controller IP in the top level. You can have as many as can fit within the EMIF I/O resources of your selected device. And some resources can be shared between multiple interfaces to allow for more interfaces.
2) As mentioned above, it depends on the number of ranks for each DIMM. If the DIMMs are only single or dual rank, you can get away with only a single instance of the EMIF IP. If you require in total more than 4 CS signals, you need an additional EMIF instance.
3) As mentioned, a single dual-rank DIMM is a single DIMM in a slot that requires two CS signals. Read "DIMM Options" on page 226 and the notes at the bottom of table 261 in the guide you linked.
Thanks for the reply. It was of great help!
One other clarification would really help i.e., suppose i have two DIMM's, can each DIMM be connected to separate EMIF IP?
Yes, you can use separate controllers for separate DIMMs.
Max bit width depends on your target device. But if you have the pins and the device supports it, you could have two separate 144 bit interfaces.