Issue Description: I enabled 'Debug Toolkit' feature of P-tile AVST PCIe Hard IP in Quartus and could see the PCIe endpoint in Linux, but No DUT listed in System Console after Load Design.
Tried Quartus Pro 20.1/20.2/21.1, same issue.
Hardware: AGF dev kit
Do you see any other error message in debug toolkit ?
Also, have you done following as explained in P-tile user guide doc (page 164) ?
The reconfig_clk should be around 100MHz to 125MHz.
I do not see any errors in debug toolkit as blow:
As for the assignment, I assign a 100M clk to xcvr_reconfig_clk_clk, but for p0_hip_reconfig_clk_clk, I quartus assign it to 0 after platform designer generation as below:
I check the toolkit clk and reset signals as below:
Can you try pull "p0_hip_reconfig_clk_clk" to your top level project file and assign to input clock pin as suggested by the P-tile user guide doc ?
Also ensure your Agilex dev kit board is supplying correct clocking frequency to both the reconfig_clk pins.
The other thing that you can check is to verify reconfig_reset signal if available is not stuck in reset also.