Cyclone V - Differential Pair Pin Assignment 1.5V PCML fitter error

[TerraX]

When creating a new Quartus project similar to a demo example, I am trying to place XCVR pins in a blank project and getting an error from the 1.5V PMCL differential pins (HSMC_GXB_RX_p0 and HSMC_GXB_TX_p0 for example).

Why am I getting this fitter error and do I need some minimum of connections to support the differential pins, and if that is the case what is the minimum code I need to declare these pins in a new project so it compiles?

I believe I have the IO standard correctly set to 1.5V PCML and Pins set to the recommended pins in the User's Guide and there are no other pins conflicting that I can see in the QSF file.

Compiler Error:

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
    Error (175020): The Fitter cannot place logic pin in region (0, 11) to (0, 11), to which it is constrained, because there are no valid locations in the region for logic of this type.
        Info (14596): Information about the failing component(s):
            Info (175028): The pin name(s): HSMC_GXB_TX_p0
        Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
            Error (184016): There were not enough differential output pin locations available (1 location affected)
                Info (175029): pin containing PIN_AE4
            Info (175015): The I/O pad HSMC_GXB_TX_p0 is constrained to the location PIN_AE4 due to: User Location Constraints (PIN_AE4)
                Info (14709): The constrained I/O pad is contained within this pin
    Error (175020): The Fitter cannot place logic pin in region (0, 14) to (0, 14), to which it is constrained, because there are no valid locations in the region for logic of this type.
        Info (14596): Information about the failing component(s):
            Info (175028): The pin name(s): HSMC_GXB_RX_p0
        Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
            Error (184016): There were not enough differential input pin locations available (1 location affected)
                Info (175029): pin containing PIN_AD2
            Info (175015): The I/O pad HSMC_GXB_RX_p0 is constrained to the location PIN_AD2 due to: User Location Constraints (PIN_AD2)
                Info (14709): The constrained I/O pad is contained within this pin

 .QSF file output:

set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY CPL_HDL
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:00:27  JUNE 13, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE CPL_HDL.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES ON
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p0
set_location_assignment PIN_AD2 -to HSMC_GXB_RX_p0
set_location_assignment PIN_AD1 -to "HSMC_GXB_RX_p0(n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p0
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_CONVST
set_location_assignment PIN_AB22 -to ADC_CONVST
set_location_assignment PIN_AA21 -to ADC_SCK
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_SCK
set_location_assignment PIN_Y10 -to ADC_SDI
set_location_assignment PIN_W10 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_SDO
set_location_assignment PIN_D7 -to AUD_ADCDAT
set_location_assignment PIN_C7 -to AUD_ADCLRCK
set_location_assignment PIN_E6 -to AUD_BCLK
set_location_assignment PIN_H10 -to AUD_DACDAT
set_location_assignment PIN_G10 -to AUD_DACLRCK
set_location_assignment PIN_D6 -to AUD_XCK
set_location_assignment PIN_R20 -to CLOCK_50_B5B
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_ADCDAT
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_ADCLRCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_BCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_DACDAT
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_DACLRCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_XCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_B5B
set_location_assignment PIN_N20 -to CLOCK_50_B6A
set_location_assignment PIN_H12 -to CLOCK_50_B7A
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_B6A
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50_B7A
set_location_assignment PIN_M10 -to CLOCK_50_B8A
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50_B8A
set_location_assignment PIN_U12 -to CLOCK_125_p
set_instance_assignment -name IO_STANDARD LVDS -to CLOCK_125_p
set_location_assignment PIN_V12 -to "CLOCK_125_p(n)"
set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF
set_location_assignment PIN_AE4 -to HSMC_GXB_TX_p0
set_location_assignment PIN_AE3 -to "HSMC_GXB_TX_p0(n)"
set_global_assignment -name SMART_RECOMPILE OFF
set_location_assignment PIN_AB24 -to CPU_RESET_n
set_location_assignment PIN_Y18 -to HEX0[6]
set_location_assignment PIN_Y19 -to HEX0[5]
set_location_assignment PIN_Y20 -to HEX0[4]
set_location_assignment PIN_W18 -to HEX0[3]
set_location_assignment PIN_V19 -to HEX0[0]
set_location_assignment PIN_V18 -to HEX0[1]
set_location_assignment PIN_V17 -to HEX0[2]
set_location_assignment PIN_AA18 -to HEX1[0]
set_location_assignment PIN_AD26 -to HEX1[1]
set_location_assignment PIN_AB19 -to HEX1[2]
set_location_assignment PIN_AE26 -to HEX1[3]
set_location_assignment PIN_AE25 -to HEX1[4]
set_location_assignment PIN_AC19 -to HEX1[5]
set_location_assignment PIN_AF24 -to HEX1[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CPU_RESET_n
set_location_assignment PIN_B7 -to I2C_SCL
set_location_assignment PIN_G11 -to I2C_SDA
set_instance_assignment -name IO_STANDARD "2.5 V" -to I2C_SCL
set_instance_assignment -name IO_STANDARD "2.5 V" -to I2C_SDA
set_location_assignment PIN_P11 -to KEY[0]
set_location_assignment PIN_P12 -to KEY[1]
set_location_assignment PIN_Y15 -to KEY[2]
set_location_assignment PIN_Y16 -to KEY[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

[Kshitij_Intel]

Hi,

Tx and Rx are two separate clock domains. Based on two remote transactions there will be CDC problem.

You need to synchronize the data. Reconstruct the data with the valid SDI frame and then re-transmit again.

Add signal tap on relevant signals including clocks.

Thank you

Kshitij Goel

[TerraX]

So I should:

1. Instantiate SDI_II as Receiver only, Do I need to include the Protocol option?

2. Instantiate SDI_II as Transmitter only, Do I need to include the Protocol option?

3. Instantiate Intel_PLL as Fractional, 1 Output Clk, Frequency 74.25MHz.

4. Create Logic block to glue the rx_dataout[19..0] to the tx inputs: tx_datain[19..0], tx_datain_valid, tx_dataout_valid.

5. Connect the REFCLK_p0 to xcvr_refclk for the Receiver.

6. Connect the same REFCLK_p0 to the xcvr_refclk for the Transmitter.

7. Connect the PLL 74.25MHz clock to both the Receiver and the Transmitter and the Glue Logic Block.

Sound right?

Sincerely,

Terra

[Kshitij_Intel]

Hi Terra,

Any update on this.

Thank you

Kshitij Goel

[TerraX]

You did not answer my question, is there someone else I can talk to?

[Kshitij_Intel · Accepted solution]

Hi Terra,

I have told you earlier, you cannot directly connect, Please design custom logic to reconstruct the word. First correct your design then try to compile.

Thank you

Kshitij Goel