I want to confirm cyclone V FPGA specifications.
I think Cyclone V FPGA monitoring power supplies should power up within Power supply ramp time (tramp). as per the cyclone V datasheet, in standard POR type this ramp time is from 200us to 100ms. what if the power supply ramp time is less than 200us?. FPGA complete its configuration successfully even if the supply ramp time is less than the minimum ramp time from datasheet? if not how often FPGA configuration may fail?
Please refer to Cyclone V device handbook vol1 10-5.
If t_RAMP not meet, configuration may fail.
We don't offer fail probability, and please follow the t_RAMP spec in datasheet.