How to assign memory bits?

[Tomoya3]

I have created a TrueDualPortMemory in VerilogHDL.
I can't assign reg to memorybit.

reg [15:0]mem_a16_h[7:0];

I used Assignment Editor but it did not work.
How to assign it?

FPGA:10M04SCU
Quartus Prime Lite Edition 20.1

[ShengN_Intel]

Hi,

Check this link https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/logicops/logicops/def_auto_ram_recognition.htm#:~:text=A%20logic%20option%20that%20allows,the%20functionality%20of%20the%20design.

This option must be assigned to a design entity or it is ignored check screenshot below:

Btw, this option is turned on by default as global assignment in Assignments -> Settings -> Advanced Settings (Synthesis)

Thanks,

Best Regards,

Sheng

[sstrell]

Yes as long as you've used a template or followed the recommended coding guidelines (https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/recommended-design-practices.html), RAM blocks are inferred and used automatically.  That assignment is more often used to *prevent* using on-chip RAM for a memory, usually in cases where you don't need the performance of a dedicated RAM block, devoting the actual RAM blocks for more critical functions.

[ShengN_Intel]

Hi,

Do you have any further update or concern on this thread?

Thanks,

Regards,

Sheng

[Tomoya3]

Thank you very much.

I understand that the ”Auto RAM Replacement logic option” is except MAXseries devices.

I would like to design using IP.

Regards

[ShengN_Intel]

Hi,

Does the problem being resolved if Auto RAM Replacement is assigned to the design entity of IP that mentioned in the previous post link community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-assign-memory-bits/m-p/1580782#M27049

Thanks,

Sheng