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I have created a TrueDualPortMemory in VerilogHDL.
I can't assign reg to memorybit.
I used Assignment Editor but it did not work.
How to assign it?
FPGA:10M04SCU
Quartus Prime Lite Edition 20.1
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Hi,
This option must be assigned to a design entity or it is ignored check screenshot below:
Btw, this option is turned on by default as global assignment in Assignments -> Settings -> Advanced Settings (Synthesis)
Thanks,
Best Regards,
Sheng
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Yes as long as you've used a template or followed the recommended coding guidelines (https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/recommended-design-practices.html), RAM blocks are inferred and used automatically. That assignment is more often used to *prevent* using on-chip RAM for a memory, usually in cases where you don't need the performance of a dedicated RAM block, devoting the actual RAM blocks for more critical functions.
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Hi,
Do you have any further update or concern on this thread?
Thanks,
Regards,
Sheng
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Thank you very much.
I understand that the ”Auto RAM Replacement logic option” is except MAXseries devices.
I would like to design using IP.
Regards
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Hi,
Does the problem being resolved if Auto RAM Replacement is assigned to the design entity of IP that mentioned in the previous post link community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-assign-memory-bits/m-p/1580782#M27049
Thanks,
Sheng

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