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I'm using Quartus to program a Cyclone V FPGA and it instantiates redundant feeder logic I'd like to remove (pic). The verilog that it does this for is very simple; it's just a reg that's driven by a delay line (pair of inverter gates):

wire [8:0] DL_0;

reg [8:0] R_0;

DelayLine #(1) DLIN_0 (enable, DL_0[0]);

genvar k_0;

generate

for (k_0=1; k_0<9; k_0=k_0+1) begin : generate_rdels_0

DelayLine #(1) DLK_0 (

.in(DL_0[k_0-1]),

.out(DL_0[k_0])

);

end

endgenerate

genvar j_0;

generate

for (j_0=0; j_0<9; j_0=j_0+1) begin : generate_regs_0

always @(negedge DL_0[j_0]) begin

R_0[j_0] <= node[0];

end

end

endgenerate

Can anyone help me with this? I've played around with the settings for the compiler and fitter to no avail (turned off register duplication, etc.)

Thanks!

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Hi,

Could you provide the design.qar for investigation? What is the software version?

Thanks.

Best regards,

KhaiY

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Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

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hi NChar7,

i am FPGA beginer, i also got this '~feeder', but i don't know what it stands for? I'm confused where this '~feeder' comes from and what does it mean?

Did you get any ideal about it?

Thanks

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