Stratix 10 SX Evaluation Board: SI5341 Output 2 CLK Frequency?

[Vhe]

Does anyone know the clock frequency of output 2 of the SI5341 on the Stratix10 SX Evaluation Board? It is on page 34 of the attached schematic. 

[Farabi]

Hello, 

This is to let you know that I am investigating your request. 

I will get back to you once I have the solution for your request. 

regards,

Farabi

[vandeje]

Also, can you confirm the voltage standard for the output differential pair in question?

Is it LVDS like the other differential output pairs are labeled?

[Vhe]

Differential LVPECL

[Farabi]

Hello,

Si5431 can generate multiple clock standard, but currently it is programmed to generate LVPECL. Register value as in page 23 of this document, link : https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/reference-manuals/Si5341-40-D-RM.pdf

The frequency can be set using BTS (Board Test System), link : https://www.intel.com/content/www/us/en/docs/programmable/683303/current/the-clock-control.html (Chapter 5.3.10).

regards,

Farabi

[Farabi]

Hello,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,

Farabi