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Stratix-III DSP kit

Altera_Forum
Honored Contributor I
977 Views

Hi, I have the Stratix-III development board and was wondering what it takes to get a clock signal out of the CLOCK_SMA_OUT port? I've written some VHDL to talk to a few different ADC boards but one of these boards needs a 400MHz clock. I generate this clock with the PLL megafunction, but I can't seem to route it to the SMA. Is this even possible since the SMA would require a single ended TTL signal rather than an LVDS? 

 

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Altera_Forum
Honored Contributor I
66 Views

Problem solved.

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