What's the general recommended power supply decoupling capacitors solution for MAX10 10M50DAF256

[JohnSyu]

Hi to the community,

I'm seeking your assistance. Recently I'm trying to design with application of 10M50F256 or 10M40F256, and I have read many Intel documents such as:

1. design files expecily schematics of  Intel® MAX® 10 FPGA Development Kits(10M50D, F484 package FPGA.) , Intel® MAX® 10 FPGA Evaluation Kit(10M50D, F484 package FPGA.) 

2.  MAX® 10 Device Handbook(including Intel® MAX® 10 FPGA Configuration User Guide and so on)

3. Power Supply Integrity 

4. Power Distribution Network 

I'm not a natural English-speaker and I am particularly unfamiliar with PDN technology, and the schematics of Development Kits is for 10M50DF484, so I don't know how to use PDN 2.0 tools, I am not sure how many decoupling capacitors should I use for F256 package and I am not sure for the value.

My design will not involve high-speed signals, only read and write UFM. So I want to know the exactly power supply decoupling capacitors solution for MAX10 10M50DAF256 or 10M40F256. Is there any reference design for 10M50DAF256 or 10M40F256?

p.s. The decoupling capacitor I am referring to is the device shown in the following figure

[Ash_R_Intel]

Hi,

Number of decoupling capacitors depend upon the current consumption of the design. The frequency of the design, blocks used, number of IOs etc. affect the current consumption. The end goal is to achieve a low impedance profile (Zeff) below the target impedance (ZTARGET) up to the desired frequency (Ftarget or Feffective).

To understand more, refer to several documentations available on the website: Power Distribution Network (PDN) | Intel.

Regards